ORIN AGX (JP36.4) PCIE CLOCK Polarity

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
1

Hi,
I am aware that PCIe Data lanes support polarity inversion (N and P) as written in the Design Guide.
What about the PCIe Clock?

2

Hi,

If you are designing a custom base board, then it means some adaptation configurations are needed.
Otherwise, your board may not work fine.

For Orin AGX series, you could refer to below document
https://docs.nvidia.com/jetson/archives/r36.3/DeveloperGuide/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=universal%20serial%20bus#jetson-agx-orin-platform-adaptation-and-bring-up
(please be aware that above link is for rel-36.3/jetpack6.0)

This document includes below configuration

  1. pinmux change & GPIO configuration
  2. EEPROM change as most custom boards do not have an EEPROM on it.
  3. Kernel porting
  4. PCIe configuration
  5. USB configuration
  6. MGBE configuration
  7. RGMII configuration

Thanks!

5

It is not supported as you can see in PCIe spec.