Proper SRNS PCIe implementation Jetson AGX Orin

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
1

Good morning everyone,

I am about to implement SRNS clocking for the PCIe communication between two different Jetson AGX Orin modules.

As so, I was wondering how to provide the two different clock sources for each module. As stated by the design guide, one module should act as the root and the other as the endpoint.

Now, as I have noted from the following post: Orin AGX SRNS clocking - Jetson & Embedded Systems / Jetson AGX Orin - NVIDIA Developer Forums, “we would need to connect an HCSL-compatible 100MHz oscillator output(without SSC) to UPHY_REFCLK0_N/P (at endpoint only) and PEX_CLK5_N/P (at Root port and Endpoint) shall be left open.”

However, the following post: Orin AGX 100MHz PCIe reference clock - Jetson & Embedded Systems / Jetson AGX Orin - NVIDIA Developer Forums shows the following image:

image
image747×641 59 KB

Giving the impression that two separate external reference clocks can should be used for SRNS clocking, instead of just one for the EP, and using the internal clock for the RP.

Which of those is the correct one?

Thank you in advance!

2

Hi,

If you are designing a custom base board, then it means some adaptation configurations are needed.
Otherwise, your board may not work fine.

For Orin AGX series, you could refer to below document
https://docs.nvidia.com/jetson/archives/r36.3/DeveloperGuide/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=universal%20serial%20bus#jetson-agx-orin-platform-adaptation-and-bring-up
(please be aware that above link is for rel-36.3/jetpack6.0)

This document includes below configuration

  1. pinmux change & GPIO configuration
  2. EEPROM change as most custom boards do not have an EEPROM on it.
  3. Kernel porting
  4. PCIe configuration
  5. USB configuration
  6. MGBE configuration
  7. RGMII configuration

Thanks!

3

Hello,

The document you just provided gives software configuration. I am asking about SRNS clocking implementation in hardware.

Thank you.

5

As said in that topic: Both common mode and SRNS are supported.

7

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