hi
is it possible to enable Orin PCIe sperate Refclk? and disable its current common Refclk??
does anyone know whether Orin supports SRIS/SRNS?
Hi,
Orin supports SRNS but no SRIS. But extra software configuration is needed.
This part seems not in document. I will make a summary and update.
- If you want to use SRNS, then you have to disable SSC(on both EP and RP side)
Please convert your bpmp dtb back to dts by using dtc tool and add below one.
diff --git a/include/parts/uphy/3701-0000-3737-0000-uphy.dtsi b/include/parts/uphy/3701-0000-3737-0000-uphy.dtsi
index 4eb42bd..8bbaea9 100644
--- a/include/parts/uphy/3701-0000-3737-0000-uphy.dtsi
+++ b/include/parts/uphy/3701-0000-3737-0000-uphy.dtsi
@@ -10,6 +10,17 @@
/ {
+ clocks {
+ clock@pllnvhs {
+ clk-id = <TEGRA234_CLK_PLLNVHS>;
+ disable-spread = <1>;
+ };
+
+ clock@pllgbe {
+ clk-id = <TEGRA234_CLK_PLLGBE>;
+ disable-spread = <1>;
+ };
+ };
/*
* HSIO UPHY (UPHY0)
* Option | Lane 0 | Lane 1 | Lane 2 | Lane 3 | Lane 4 Lane 5 | Lane 6 Lane 7 |
Also, please be aware that Disabling PCIe SSC will make products hard to pass EMC tests.
- There is a property "nvidia,enable-srns” for kernel dtb. You have to add this in both EP and RP PCIe controller DT.
hi @WayneWWW
thanks for your answer, but we changed the dts, and added “nvidia,enable-srns”, seems SRNS doesn’t work, would you check what else we should change in kernel and in dts??
Disabling ssc is also needed if you want to enable SRNS. Are you sure you get the points?
I am not talking about you can only enable it by adding one line in kernel dts. You have to change bpmp dtb too.
Also, is your use case including jetson as EP? or your EP is other kind of devices?
yes, we added disabling SSC by adding:
+ clocks {
+ clock@pllnvhs {
+ clk-id = <0xf3>;
+ disable-spread = <1>;
+ };
+
+ clock@pllgbe {
+ clk-id = <0x13f>;
+ disable-spread = <1>;
+ };
+ };
Are you sure you add it to the correct file?
BTW, you can try to clean up the format first…
this is code block
Hi,
I don’t need to read your file because it is obvious wrong.
bpmp dtb is not same as kernel dtb. They are different files. When you shared the kernel dts only, it is wrong.
Please check your board config and there is a dtb file with “bpmp” string inside, that one is the file you need to add SSC disable code.
Hi
- Added the SRNS enable setting in the RP & EP
- Disabled the spread as I see in the previous dicussion through tegra234-p3701-0000-p3737-0000.dts
But unfortunately looks like no luck with SRNS enabled. Do you see any mistakes in the above ?
Hi,
bpmp dtb is not tegra234-p3701-0000-p3737-0000.dts…
Check your board config file to check what that file is.
If you don’t know what board config file is, please ask.
extlinux/extlinux.conf
TIMEOUT 30
DEFAULT primary
MENU TITLE L4T boot options
LABEL primary
MENU LABEL primary kernel
LINUX /boot/Image
FDT /boot/dtb/**kernel_tegra234-p3701-0000-p3737-0000.dtb**
INITRD /boot/initrd
APPEND ${cbootargs} root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 mminitt
_loglevel=4 console=ttyTCU0,115200 console=ttyAMA0,115200 console=tty0 firmware__
class.path=/etc/firmware fbcon=map:0 net.ifnames=0 nv-auto-config
so kernel_tegra234-p3701-0000-p3737-0000.dtb is not what you meant, where is the “bpmp dtb”??
linux@orin1:/boot$ ls *.dtb
kernel_tegra234-p3701-0000-p3737-0000.dtb
tegra194-p2888-0001-p2822-0000.dtb
tegra194-p2888-0001-p2822-0000-maxn.dtb
tegra194-p2888-0004-e3900-0000.dtb
tegra194-p2888-0008-p2822-0000.dtb
tegra194-p2888-0008-p2822-0000-maxn.dtb
tegra194-p3668-0000-p3509-0000.dtb
tegra194-p3668-0001-p3509-0000.dtb
tegra194-p3668-all-p3509-0000.dtb
tegra234-p3701-0000-as-p3767-0000-p3737-0000.dtb
tegra234-p3701-0000-as-p3767-0001-p3737-0000.dtb
tegra234-p3701-0000-as-p3767-0003-p3737-0000.dtb
tegra234-p3701-0000-as-p3767-0004-p3737-0000.dtb
tegra234-p3701-0000-p3737-0000.dtb
tegra234-p3701-0002-p3711-0000.dtb
tegra234-p3701-0002-p3740-0002-b01.dtb
tegra234-p3701-0002-p3740-0002.dtb
tegra234-p3701-0004-p3737-0000.dtb
Oh right… I was thinking for kernel device tree but I realize I was wrong since the boot loader (or early FW) shall ideally do the clock config as that’s the 1st point accessing the device.
Could you please help to share direction on how can I identify and modify board config file to disable spread ? Where is the file located?
Hi,
Did you two ever flash your jetson with sdkamanger or directly using BSP before?
What I am talking about is on the x86 host PC but not your device. Searching on your jetson won’t find the file.
it is this dtb file: bootloader/t186ref/tegra234-bpmp-3701-0005-3737-0000.dtb
sudo ./flash.sh jetson-agx-orin-devkit mmcblk0p1
does this command re-flash rootfs as well?
Hi,
Basically, I don’t “memorize” what files will be in use for a board because there are too many boards on my side to check. Instead, you can read the board config or the flash log (after you run flash.sh, it will print on your terminal) to see what file is in use. Even jetson orin AGX has multiple BPMP dtb too.
For example, 3701-0005 is for Orin 64GB. If you are not using this module, then you file could be different one. (as you didn’t tell what kind of module you are using, I cannot directly answer it either).
Also, flash.sh will reflash the rootfs. I don’t know what you are trying here, but flash tool is a very basic one you should learn first before trying any customization.
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