disable spread spectrum in tx2 R28.2.1

applied patches from the links

https://devtalk.nvidia.com/default/topic/1036587/jetson-tx1/what-are-best-way-for-disable-jetson-tx1-pcie-ssc-/post/5266788/#5266788

https://devtalk.nvidia.com/default/topic/1055234/jetson-tx2/pcie-not-being-recognized-tx2/post/5353473/#5353473

Not working at all…!! SSC register is not updating after applying above patches.

Please anyone from Nvidia team do reply for this support.

thanks

Please share which register did you check. Thanks.

Have you tried this method from the thread you filed?

https://devtalk.nvidia.com/default/topic/1066076/jetson-tx2/how-to-disable-ssc-/?offset=2#5398648

0x05043000

yes !!

I updated bpmp dtb from “/L4T/bootloader/”

generated signed dtb by using flag “–no-flash”.

then copied generated signed dtb to “/L4T/bootloader/tegra186/signed/”

then flashed using flash.sh bpmp-fw-dtb.

refferred link :-
https://devtalk.nvidia.com/default/topic/1025480/jetson-tx1/disable-spread-spectrum-ssc-on-the-tx1-with-a-28-1-release-/post/5400702/#5400702

  1. Please do not push the pcie driver patch to your driver. That is for TX1 only.
  2. I don’t get the point here. Why not just put the updated dtb to Linux_for_Tegra/bootloader/t186ref and flash?
    You don’t need to do those “–no-flash” and put signed dtb to the folder.

Hi,

when I tried to flash bpmp dtb using following “sudo ./flash -k bpmp-fw-dtb jetson-tx2 mmcblk0p1”,
It failed throwing error "tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2_sigheader.dtb.encrypt con’t be of size zero.

I found out that signed dtb will get generated during flash script at /L4T/bootloader/signed/ but flash script for “bpmp-fw-dtb” is searching for signed dtb in /L4T/bootloader/t186ref/signed/

for this reason I had to generate signed dtb & copy from /L4T/bootloader/signed/ to /L4T/bootloader/t186ref/signed/ then flash It.

One point I’m not getting. when I update the DTB why REG read is not updating & why SSC is not disabled !!.

Is that bpmp dtb patch is tested one ??

clocks {
        clock@plle {
			clk-id = <0x200>;
			pll_freq_table = <0x249f000 0x5f5e100 0x2 0x7d 0x18 0xffffffff 0xffffffff 0xffffffff 0xffffffff>;
		   };
      };

Please help me!
Thank You!

That sounds correct. Could you share how you update the bpmp dtb?

  1. I extracted the tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb using DTC command.

  2. pasted the above mentioned patch under clocks node at the end as shown below

clocks {

		init {
			i2c1 = <0x2f 0x10d 0x0 0x0>;
			i2c2 = <0xda 0x10d 0x0 0x0>;
			i2c3 = <0x4b 0x10d 0x0 0x0>;
			i2c4 = <0x56 0x10d 0x0 0x0>;
			i2c6 = <0x7d 0x10d 0x0 0x0>;
			i2c7 = <0xb6 0x10d 0x0 0x0>;
			i2c8 = <0xdb 0x10d 0x0 0x0>;
			i2c9 = <0xb7 0x10d 0x0 0x0>;
			i2c_slow = <0x5c 0x260 0x0 0x0>;
			aon_i2c_slow = <0xdd 0x260 0x0 0x0>;
			vi_i2c = <0x85 0x10d 0x0 0x0>;
			i2c12 = <0xb8 0x10d 0x0 0x0>;
			i2c13 = <0xb9 0x10d 0x0 0x0>;
			i2c14 = <0xba 0x10d 0x0 0x0>;
			xusb = <0x6f 0x10d 0x6146580 0x0>;
			xusb_core_dev = <0xf3 0x10d 0x6146580 0x0>;
			xusb_falcon = <0xf4 0x10d 0xc28cb00 0x0>;
			xusb_fs = <0xf5 0x112 0x2dc6c00 0x0>;
			xusb_core_ss = <0xf2 0x113 0x7270e00 0x0>;
			pllc4_vco = <0x20c 0x0 0x2faf0800 0x0>;
			pllc4_out0 = <0x114 0x0 0xbebc200 0x0>;
			hsic_trk = <0xf1 0x0 0x927c00 0x0>;
			pll_a1 = <0x20d 0x0 0x23c34600 0x0>;
			aclk = <0x111 0x20d 0x11e1a300 0x0>;
			isp = <0x32 0x236 0x249f0000 0x0>;
			nvdec = <0x81 0x237 0x2932e000 0x0>;
			nvenc = <0x83 0x238 0x2932e000 0x0>;
			nvjpg = <0x82 0x239 0x1dc13000 0x0>;
			se0 = <0x67 0x0 0x0 0x1>;
			se1 = <0x67 0x23b 0x1ee62800 0x0>;
			tsec0 = <0x51 0x0 0x0 0x20000>;
			tsec1 = <0x51 0x23c 0x1c9c3800 0x0>;
			tsecb = <0x89 0x23d 0x1c9c3800 0x0>;
			vi = <0x33 0x23e 0x21301800 0x0>;
			vic = <0x7f 0x23f 0x249f0000 0x0>;
			nvdisplayhub = <0x9e 0x10d 0x18519600 0x0>;
			nafll_bpmp = <0x235 0x0 0x124f8000 0x0>;
			bpmp_apb = <0xc7 0x10d 0x0 0x0>;
			bpmp_cpu_nic = <0xc5 0x235 0x0 0x0>;
			hda = <0x66 0x10d 0x30a32c0 0x0>;
			hda2codec_2x = <0x58 0x10d 0x2dc6c00 0x0>;
			extperiph1 = <0x59 0x10d 0x0 0x0>;
			extperiph2 = <0x5a 0x10d 0x0 0x0>;
			sce_cpu_nic = <0xe4 0x23a 0x1b7a4d40 0x0>;
			sce_apb = <0xe6 0x10d 0x6146580 0x0>;
			aon_cpu = <0xd0 0x264 0x249f000 0x1>;
			aon_apb = <0xd6 0x264 0x249f000 0x1>;
			uart_fst_mipical = <0x7e 0x10d 0x40d9900 0x0>;
			aud_mclk = <0x7c 0x0 0x1770000 0x0>;
			pllnvcsi = <0x20e 0x0 0x1ad27480 0x0>;
			pll_a = <0x10f 0x0 0xf60c480 0x0>;
			axi_cbb = <0x95 0x234 0x6146580 0x0>;
			plla_out1 = <0x120 0x0 0x8f0d180 0x0>;
			ape = <0x69 0x120 0x0 0x20000>;
			host1x = <0x39 0x0 0x0 0x1>;
		};

		clock@bpmp_apb {
			clk-id = <0xc7>;
			allowed-parents = <0x10d 0x260 0x261>;
			mrq_hide = <0x1>;
		};

		clock@sce_apb {
			clk-id = <0xe6>;
			allowed-parents = <0x10d 0x260 0x261>;
		};

		clock@bpmp_nic {
			clk-id = <0x11f>;
			mrq_hide = <0x1>;
		};

		clock@axi_cbb {
			clk-id = <0x95>;
			allowed-parents = <0x234>;
		};

		clock@bpmp_cpu_nic {
			clk-id = <0xc5>;
			allowed-parents = <0x235>;
			mrq_hide = <0x1>;
		};

		clock@isp {
			clk-id = <0x32>;
			allowed-parents = <0x236>;
		};

		clock@nvdec {
			clk-id = <0x81>;
			allowed-parents = <0x237>;
		};

		clock@nvenc {
			clk-id = <0x83>;
			allowed-parents = <0x238>;
		};

		clock@nvjpg {
			clk-id = <0x82>;
			allowed-parents = <0x239>;
		};

		clock@sce_cpu_nic {
			clk-id = <0xe4>;
			allowed-parents = <0x23a>;
		};

		clock@se {
			clk-id = <0x67>;
			allowed-parents = <0x23b>;
		};

		clock@tsec {
			clk-id = <0x51>;
			allowed-parents = <0x23c>;
		};

		clock@tsecb {
			clk-id = <0x89>;
			allowed-parents = <0x23d>;
		};

		clock@vi {
			clk-id = <0x33>;
			allowed-parents = <0x23e>;
		};

		clock@vic {
			clk-id = <0x7f>;
			allowed-parents = <0x23f>;
		};

		clock@i2c_slow {
			clk-id = <0x5c>;
			allowed-parents = <0x260>;
		};

		clock@aon_i2c_slow {
			clk-id = <0xdd>;
			allowed-parents = <0x260>;
		};

		clock@nafll_axi_cbb {
			clk-id = <0x234>;
			mrq_hide = <0x1>;
		};

		clock@nafll_bpmp {
			clk-id = <0x235>;
			mrq_hide = <0x1>;
		};

		clock@nafll_isp {
			clk-id = <0x236>;
			mrq_hide = <0x1>;
		};

		clock@nafll_nvdec {
			clk-id = <0x237>;
			mrq_hide = <0x1>;
		};

		clock@nafll_nvenc {
			clk-id = <0x238>;
			mrq_hide = <0x1>;
		};

		clock@nafll_nvjpg {
			clk-id = <0x239>;
			mrq_hide = <0x1>;
		};

		clock@nafll_sce {
			clk-id = <0x23a>;
			mrq_hide = <0x1>;
		};

		clock@nafll_se {
			clk-id = <0x23b>;
			mrq_hide = <0x1>;
		};

		clock@nafll_tsec {
			clk-id = <0x23c>;
			mrq_hide = <0x1>;
		};

		clock@nafll_tsecb {
			clk-id = <0x23d>;
			mrq_hide = <0x1>;
		};

		clock@nafll_vi {
			clk-id = <0x23e>;
			mrq_hide = <0x1>;
		};

		clock@nafll_vic {
			clk-id = <0x23f>;
			mrq_hide = <0x1>;
		};

		clock@nafll_gpu {
			clk-id = <0x241>;
			mrq_hide = <0x1>;
		};

		clock@nafll_bcpu {
			clk-id = <0x243>;
			mrq_hide = <0x1>;
		};

		clock@nafll_mcpu {
			clk-id = <0x242>;
			mrq_hide = <0x1>;
		};

		clock@hda2codec_2x {
			clk-id = <0x58>;
			allow_fractional_divider = <0x1>;
		};

		clock@spdif_in {
			clk-id = <0x2c>;
			allow_fractional_divider = <0x1>;
		};

		clock@uarta {
			clk-id = <0x37>;
			allow_fractional_divider = <0x1>;
		};

		clock@uartb {
			clk-id = <0x38>;
			allow_fractional_divider = <0x1>;
		};

		clock@uartc {
			clk-id = <0xd7>;
			allow_fractional_divider = <0x1>;
		};

		clock@uartd {
			clk-id = <0x4d>;
			allow_fractional_divider = <0x1>;
		};

		clock@uarte {
			clk-id = <0xc2>;
			allow_fractional_divider = <0x1>;
		};

		clock@uartf {
			clk-id = <0xc3>;
			allow_fractional_divider = <0x1>;
		};

		clock@uartg {
			clk-id = <0xd8>;
			allow_fractional_divider = <0x1>;
		};

		clock@sdmmc2 {
			clk-id = <0x35>;
			allow_fractional_divider = <0x1>;
		};

		clock@plle {
			clk-id = <0x200>;
			pll_freq_table = <0x249f000 0x5f5e100 0x2 0x7d 0x18 0xffffffff 0xffffffff 0xffffffff 0xffffffff>;
		};
	};
  1. compiled the extracted dts to dtb ( tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb).

  2. generated signed dtb using “–no-flash” command

  3. flashed the bpmp-fw-dtb.

thanks

How about using the full flash instead of using “-k bpmp-fw-dtb”?

Thank you so much !!

full flash worked !!

the modified DTB for tx2 is “/L4T/bootloader/t186ref/tegra-186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb”

the modified DTB for tx2i is “/L4T/bootloader/t186ref/tegra-186-a02-bpmp-storm-p3489-a00-00-ta795sa-ucm1.dtb”

Hello,

In JetPack 4.2.1, the original jetson-tx2i.conf contains the following line:

BPFDTB_FILE=tegra-186-a02-bpmp-storm-p3489-a00-00-ta795sa-ucm1.dtb

If I understand correctly, this should disable spread spectrum.

Am I right ?

I did a full flash with:
sudo ./flash.sh jetson-tx2i mmcblk0p1

After reboot, should I expect spread spectrum to be disabled ?

Thank you in advance,
Zvika

One way to check if SSC is enabled/disabled in a platform is to read the value from address 0x05043000.
If bit-12 is
0 -> SSC enabled (with default build, we would get a value like 0x20010025 where bit-12 is ‘0’)
1 -> SSC disabled (after applying above patch, the value would be 0x20011C25 where bit-12 is ‘1’)

Thank you very much !