Hi guys,
How can I disable PCIe SSC on Xavier? Is it possible to disable it while running?
thanks
It is not possible to disable it while running.
Although you can disable it through the BPMP-FW’s DT modification.
Following change can be used to disable the spread for C0, C1, C3 & C4 controllers
git repo: $TOP/platform/bpmp-t19x/
diff --git a/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi b/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi
index 7f1a3fd…b0fa711 100644 (file)
--- a/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi
+++ b/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi
@@ -1,4 +1,4 @@
-
+#include <mach-t194/clk-t194.h>
/ {
uphy {
status = "okay";
@@ -6,4 +6,11 @@
ufs-config = "UFS_x1_L1";
nvhs-owner = "PCIE";
};
+ clocks {
+ clock@plle {
+ clk-id = <TEGRA194_CLK_PLLE>;
+ /* disable ssc on PLLE */
+ pll_freq_table = <38400000 100000000 2 125 24 (-1) (-1) (-1) (-1)>;
+ };
+ };
};
Following change can be used to disable the spread for C5 controller
diff --git a/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi b/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi
index 7f1a3fd..b63d02e 100644 (file)
--- a/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi
+++ b/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi
@@ -1,4 +1,4 @@
-
+#include <mach-t194/clk-t194.h>
/ {
uphy {
status = "okay";
@@ -6,4 +6,11 @@
ufs-config = "UFS_x1_L1";
nvhs-owner = "PCIE";
};
+ clocks {
+ clock@pllnvhs {
+ clk-id = <TEGRA194_CLK_PLLNVHS>;
+ /* disable ssc on PLLNVHS */
+ pll_freq_table = <38400000 100000000 2 125 24 (-1) (-1) (-1) (-1)>;
+ };
+ };
};
Can you please guide me where are these files located? Are these files already in xavier’s filesystem or is it necessary to recompile kernel? I can not find them in nvidia_sdk folder created by NvidiaSDK manager.
thanks
Hi,
Please open the Linux_for_Tegra folder on your host and locate the dtb file which has bpmp keywords first.
Hello, thank you for quick response. These are all the files containing bpmp keyword. Which is the correct one?
./bootloader/t186ref/tegra194-a02-bpmp-p2888-as-galen-8gb.dtb
./bootloader/t186ref/tegra194-a02-bpmp-p2888-as-p3668.dtb
./bootloader/t186ref/tegra186-a02-bpmp-storm-p3489-evt-00-ta795sa-ucm1.dtb
./bootloader/t186ref/tegra186-a02-bpmp-storm-p3489-evt-00-ta795sa-ucm2.dtb
./bootloader/t186ref/tegra186-a02-bpmp-storm-p3489-a00-00-ta795sa-ucm1.dtb
./bootloader/t186ref/tegra186-a02-bpmp-storm-p3489-a00-00-ta795sa-ecc-disabled-ucm1.dtb
./bootloader/t186ref/tegra186-a02-bpmp-lightning-p3489-a00-00-te770m.dtb
./bootloader/t186ref/tegra186-a02-bpmp-quill-p3310-1000-c01-00-te770d-ucm2.dtb
./bootloader/t186ref/tegra186-a02-bpmp-p3310-1000-c01-as-0888.dtb
./bootloader/t186ref/tegra186-a02-bpmp-quill-p3310-1000-c01-00.dtb
./bootloader/t186ref/tegra186-a02-bpmp-quill-p3310-1000-c04-00.dtb
./bootloader/t186ref/tegra186-a02-bpmp-p3310-1000-c04-as-0888.dtb
./bootloader/t186ref/tegra194-a02-bpmp-p2888-a02.dtb
./bootloader/t186ref/tegra194-a02-bpmp-p3668-a00.dtb
./bootloader/t186ref/tegra186-a02-bpmp-quill-p3310-1000-c04-00-te770d-ucm2.dtb
./bootloader/t186ref/tegra194-a01-bpmp-p2888-a02.dtb
./bootloader/t186ref/tegra194-a02-bpmp-p2888-0006-a04.dtb
./bootloader/t186ref/tegra194-a02-bpmp-p2888-a01.dtb
./bootloader/t186ref/tegra186-a02-bpmp-storm-p3489-a00-00-ta795sa-ecc-disabled-ucm2.dtb
./bootloader/t186ref/tegra194-a02-bpmp-p2888-a04-maxn.dtb
./bootloader/t186ref/tegra186-a02-bpmp-quill-p3310-1000-c00-00.dtb
./bootloader/t186ref/tegra186-a02-bpmp-quill-p3310-1000-a00-00.dtb
./bootloader/t186ref/tegra186-a02-bpmp-quill-p3310-1000-c00-00-te770d-ucm2.dtb
./bootloader/t186ref/tegra186-a02-bpmp-p3310-1000-c01-as-0888-ucm2.dtb
./bootloader/t186ref/tegra186-a02-bpmp-storm-p3489-a00-00-ta795sa-ucm2.dtb
./bootloader/t186ref/tegra186-a02-bpmp-lightning-p3489-a00-00-ta795sa.dtb
./bootloader/t186ref/tegra186-a02-bpmp-p3310-1000-c04-as-0888-ucm2.dtb
./bootloader/t186ref/tegra186-a02-bpmp-storm-p3489-evt-00-ta795sa-ecc-disabled-ucm2.dtb
./bootloader/t186ref/tegra186-a02-bpmp-quill-p3310-1000-a00-00-te770d-ucm2.dtb
./bootloader/t186ref/tegra186-a02-bpmp-storm-p3489-evt-00-ta795sa-ecc-disabled-ucm1.dtb
./bootloader/t186ref/tegra194-a01-bpmp-p2888-a01.dtb
./bootloader/t186ref/tegra194-a02-bpmp-p2888-a04.dtb
./bootloader/tegra186-bpmp-quill-p3310-1000-a00-00.dtb
./bootloader/tegra194-a02-bpmp-p2888-a04.dtb
Hi,
./bootloader/tegra194-a02-bpmp-p2888-a04.dtb
This path indicates the file name get flashed into your xavier. Which is a copy.
./bootloader/t186ref/tegra194-a02-bpmp-p2888-a04.dtb
This file is the real one.
Hi,
I can find
TEGRA194_CLK_PLLE = 0x64
but I can not find what is the value of
TEGRA194_CLK_PLLNVHS
where can I find these values,
thanks
You need to recompile after applying these changes.
Path of git repo to apply changes $TOP/platform/bpmp-t19x/
to avoid any confusion please regeneration system image and do complete flashing
Hi
There is no directory in platform/bpmp-t19x/in ~/nvidia/nvidia_sdk/JetPack_4.4_DP_Linux_DP_JETSON_AGX_XAVIER/Linux_for_Tegra
where is it located?
thanks
I performed changes mentioned by vidyas in two files mentioned by WayneWWW.
~/nvidia/nvidia_sdk/JetPack_4.4_DP_Linux_DP_JETSON_AGX_XAVIER/Linux_for_Tegra
first I decompiled dtb to dts by
dtc -I dtb -O dts -o tegra194-a02-bpmp-p2888-a04.dts tegra194-a02-bpmp-p2888-a04.dtb
clock@vic {
allowed-parents = <0xcf 0xe>;
clk-id = <0xa7>;
};
clock@plle {
clk-id = <0x64>;
// disable ssc on PLLE
pll_freq_table = <38400000 100000000 2 125 24 (-1) (-1) (-1) (-1)>;
};
/*clock@pllnvhs {
clk-id = <TEGRA194_CLK_PLLNVHS>;
// disable ssc on PLLNVHS
pll_freq_table = <38400000 100000000 2 125 24 (-1) (-1) (-1) (-1)>;
};*/
init {
fuse = <0x28 0x0 0x0 0x20000>;
};
then I compiled it back to dtb by
sudo dtc -I dts -O dtb -o tegra194-a02-bpmp-p2888-a04.dtb tegra194-a02-bpmp-p2888-a04.dts
Hi,
Please forget about the file path. You just need to add those patch lines with “+” to your dts file and rebuild it as a dtb file again…
Hello,
is my procedure correct? Then I flashed jetson
sudo ./flash.sh jetson-xavier mmcblk0p1
Path is from your top of tree.
Hi
Why do you comment out it? The patch didn’t ask you to comment it out.
/clock@pllnvhs {
clk-id = <TEGRA194_CLK_PLLNVHS>;
// disable ssc on PLLNVHS
pll_freq_table = <38400000 100000000 2 125 24 (-1) (-1) (-1) (-1)>;
};/
There is error when I try to recompile it because TEGRA194_CLK_PLLNVHS is probably not defined.
Error: tegra194-a02-bpmp-p2888-a04.dts:642.18-19 syntax error FATAL ERROR: Unable to parse input tree
Hi,
is it possible to check if the SSC is disabled?
thanks
Is the modification successful?
what is the value “TEGRA194_CLK_PLLNVHS”？