Does SDIO support wifi?

gaozejun · July 8, 2020, 2:22am

I need to use one kind of sdio-wifi module named ap6398s on Xavier platform, but i want to know if sdio can support wifi on Xavier?
And I find sdio dst below :
source/kernel_src/hardware/nvidia/soc/t18x/kernel-dts/tegra186-soc/tegra186-soc-sdhci.dtsi

sdmmc1: sdhci@3400000 {
	compatible = "nvidia,tegra186-sdhci";
	reg = <0x0 0x3400000 0x0 0x210>;
	interrupts = < 0 62 0x04>;
	max-clk-limit = <204000000>;
            ddr-clk-limit = <48000000>;
	tap-delay = <11>;
	trim-delay = <5>;
	nvidia,ddr-tap-delay = <11>;
	ddr-trim-delay = <5>;
            mmc-ocr-mask = <3>;
            bus-width = <4>;
	ignore-pm-notify;
	keep-power-in-suspend;
    non-removable;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	pwrdet-support;
	pinctrl-names = "sdmmc_e_33v_enable", "sdmmc_e_33v_disable";
	pinctrl-0 = <&sdmmc1_e_33V_enable>;
	pinctrl-1 = <&sdmmc1_e_33V_disable>;
	compad-vref-3v3 = <0x1>;
	compad-vref-1v8 = <0x2>;
	nvidia,min-tap-delay = <84>;
	nvidia,max-tap-delay = <136>;
	pll_source = "pll_p";
	resets = <&tegra_car TEGRA186_RESET_SDMMC1>;
	reset-names = "sdhci";
	clocks = <&tegra_car TEGRA186_CLK_SDMMC1>,
	       <&tegra_car TEGRA186_CLK_PLLP_OUT0>,
	       <&tegra_car TEGRA186_CLK_SDMMC_LEGACY_TM>;
	clock-names = "sdmmc", "pll_p", "sdmmc_legacy_tm";
	iommus = <&smmu TEGRA_SID_SDMMC1A>;
	nvidia,en-periodic-calib;
	status = "disabled";
 };

So status = “disabled”, I want to know where status was opened “okay”?

WayneWWW · July 8, 2020, 3:27am

Hi,

We don’t verify wifi sdio on Xavier but only on TX2. Theoretically, it should work. You could enable the status in dts first.

WayneWWW · July 8, 2020, 3:30am

Also, the reference document:
kernel/kernel-4.9/Documentation/devicetree/bindings/mmc/sdhci-tegra.txt

WayneWWW · July 8, 2020, 3:53am

btw, xavier is t194 platform but not t186.

gaozejun · July 8, 2020, 3:59am

sdhci@3400000 {
	mmc-ocr-mask = <0x0>;
	cd-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(G, 7) 0>;
   non-removable;
   max-frequency = <50000000>;
	nvidia,cd-wakeup-capable;
	nvidia,vmmc-always-on;
    only-1-8-v;
	status = "okay";
};

WayneWWW · July 8, 2020, 4:01am

Below is the list from my TX2 which has TX2 enabled.

nvidia@nvidia-desktop:/proc/device-tree/sdhci@3440000$ ll
-r–r–r-- 1 root root 4 Jul 7 23:32 bus-width
-r–r–r-- 1 root root 0 Jul 7 23:32 cap-mmc-highspeed
-r–r–r-- 1 root root 0 Jul 7 23:32 cap-sd-highspeed
-r–r–r-- 1 root root 28 Jul 7 23:32 clock-names
-r–r–r-- 1 root root 24 Jul 7 23:32 clocks
-r–r–r-- 1 root root 4 Jul 7 23:32 compad-vref-1v8
-r–r–r-- 1 root root 4 Jul 7 23:32 compad-vref-3v3
-r–r–r-- 1 root root 22 Jul 7 23:32 compatible
-r–r–r-- 1 root root 4 Jul 7 23:32 ddr-clk-limit
-r–r–r-- 1 root root 4 Jul 7 23:32 ddr-trim-delay
-r–r–r-- 1 root root 0 Jul 7 23:32 force-non-removable-rescan
-r–r–r-- 1 root root 0 Jul 7 23:32 ignore-pm-notify
-r–r–r-- 1 root root 12 Jul 7 23:32 interrupts
-r–r–r-- 1 root root 0 Jul 7 23:32 keep-power-in-suspend
-r–r–r-- 1 root root 4 Jul 7 23:32 linux,phandle
-r–r–r-- 1 root root 4 Jul 7 23:32 max-clk-limit
-r–r–r-- 1 root root 4 Jul 7 23:32 mmc-ocr-mask
-r–r–r-- 1 root root 6 Jul 7 23:32 name
-r–r–r-- 1 root root 0 Jul 7 23:32 non-removable
-r–r–r-- 1 root root 4 Jul 7 23:32 nvidia,ddr-tap-delay
-r–r–r-- 1 root root 0 Jul 7 23:32 nvidia,en-periodic-calib
-r–r–r-- 1 root root 4 Jul 7 23:32 nvidia,max-tap-delay
-r–r–r-- 1 root root 4 Jul 7 23:32 nvidia,min-tap-delay
-r–r–r-- 1 root root 0 Jul 7 23:32 only-1-8-v
-r–r–r-- 1 root root 4 Jul 7 23:32 phandle
-r–r–r-- 1 root root 4 Jul 7 23:32 pinctrl-0
-r–r–r-- 1 root root 4 Jul 7 23:32 pinctrl-1
-r–r–r-- 1 root root 39 Jul 7 23:32 pinctrl-names
-r–r–r-- 1 root root 6 Jul 7 23:32 pll_source
drwxr-xr-x 11 root root 0 Jul 7 23:32 prod-settings/
-r–r–r-- 1 root root 0 Jul 7 23:32 pwrdet-support
-r–r–r-- 1 root root 16 Jul 7 23:32 reg
-r–r–r-- 1 root root 6 Jul 7 23:32 reset-names
-r–r–r-- 1 root root 8 Jul 7 23:32 resets
-r–r–r-- 1 root root 5 Jul 7 23:32 status
-r–r–r-- 1 root root 4 Jul 7 23:32 tap-delay
-r–r–r-- 1 root root 4 Jul 7 23:32 trim-delay
-r–r–r-- 1 root root 4 Jul 7 23:32 uhs-mask
-r–r–r-- 1 root root 4 Jul 7 23:32 vmmc-supply
-r–r–r-- 1 root root 4 Jul 7 23:32 vqmmc-supply

gaozejun · July 8, 2020, 5:41am

CMD Voltage is in abnormal status , you can see it in red circle.

WayneWWW · July 8, 2020, 5:47am

Hi,

I only debug from the software.

Please share your dmesg and device tree under sdhci@34000000 as text file.
It is hard to read by image.

gaozejun · July 8, 2020, 5:54am

Dst show below, whether or not is there one way to increase the ability to driver the cmd-pin?

sdmmc1: sdhci@3400000 {
compatible = “nvidia,tegra194-sdhci”;
reg = <0x0 0x3400000 0x0 0x00020000>;
interrupts = < 0 TEGRA194_IRQ_SDMMC1 0x04>;
iommus = <&smmu TEGRA_SID_SDMMC1A>;
dma-coherent;
max-clk-limit = <208000000>;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
nvidia,vqmmc-always-on;
cd-inverted;
nvidia,min-tap-delay = <96>;
nvidia,max-tap-delay = <139>;
pwrdet-support;
pinctrl-names = “sdmmc_e_33v_enable”, “sdmmc_e_33v_disable”;
pinctrl-0 = <&sdmmc1_e_33V_enable>;
pinctrl-1 = <&sdmmc1_e_33V_disable>;
ignore-pm-notify;
resets = <&bpmp_resets TEGRA194_RESET_SDMMC1>;
reset-names = “sdhci”;
pll_source = “pll_p”, “pll_c4_muxed”;
nvidia,set-parent-clk;
nvidia,parent_clk_list = “pll_p”, “pll_p”, “pll_p”, “pll_p”, “pll_p”, “pll_c4_muxed”, “pll_c4_muxed”, “pll_c4_muxed”, “pll_c4_muxed”, “pll_c4_muxed”, “NULL”;
clocks = <&bpmp_clks TEGRA194_CLK_SDMMC1>,
<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>,
<&bpmp_clks TEGRA194_CLK_PLLC4_MUXED>,
<&bpmp_clks TEGRA194_CLK_SDMMC_LEGACY_TM>;
clock-names = “sdmmc”, “pll_p”, “pll_c4_muxed”, “sdmmc_legacy_tm”;
uhs-mask = <0x08>;
nvidia,en-periodic-calib;
status = “disabled”;
};

sdhci@3400000 {
mmc-ocr-mask = <0x0>;
cd-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(G, 7) 0>;
non-removable;
nvidia,cd-wakeup-capable;
nvidia,vmmc-always-on;
compad-vref-3v3 = <0x7>;
compad-vref-1v8 = <0x7>;
only-1-8-v;
status = “okay”;
};

WayneWWW · July 8, 2020, 5:56am

Hi,

Please also share the kernel log (dmesg) too.

gaozejun · July 8, 2020, 6:01am

The kernel log must wait for some time,I just power down the board to change some resistances.

Whether or not is there one way from the software to increase the ability(the driving cureent) to driver the cmd-pin？

WayneWWW · July 8, 2020, 6:07am

Hi,

You also have difference between your dts and the dts from TX2. Please also check those.

Thanks.

gaozejun · July 8, 2020, 6:10am

I dont know TX2, can you show me the sdio-dst on TX2 platform?

WayneWWW · July 8, 2020, 6:11am

I just pasted that above… if you need any detail for specific property, please let me know.

gaozejun · July 8, 2020, 6:15am

I mean the dst such as this shown below ,that you pasted has no value.

sdmmc1: sdhci@3400000 {
compatible = “nvidia,tegra194-sdhci”;
reg = <0x0 0x3400000 0x0 0x00020000>;
interrupts = < 0 TEGRA194_IRQ_SDMMC1 0x04>;
iommus = <&smmu TEGRA_SID_SDMMC1A>;
dma-coherent;
max-clk-limit = <208000000>;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
nvidia,vqmmc-always-on;
cd-inverted;
nvidia,min-tap-delay = <96>;
nvidia,max-tap-delay = <139>;
pwrdet-support;
pinctrl-names = “sdmmc_e_33v_enable”, “sdmmc_e_33v_disable”;
pinctrl-0 = <&sdmmc1_e_33V_enable>;
pinctrl-1 = <&sdmmc1_e_33V_disable>;
ignore-pm-notify;
resets = <&bpmp_resets TEGRA194_RESET_SDMMC1>;
reset-names = “sdhci”;
pll_source = “pll_p”, “pll_c4_muxed”;
nvidia,set-parent-clk;
nvidia,parent_clk_list = “pll_p”, “pll_p”, “pll_p”, “pll_p”, “pll_p”, “pll_c4_muxed”, “pll_c4_muxed”, “pll_c4_muxed”, “pll_c4_muxed”, “pll_c4_muxed”, “NULL”;
clocks = <&bpmp_clks TEGRA194_CLK_SDMMC1>,
<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>,
<&bpmp_clks TEGRA194_CLK_PLLC4_MUXED>,
<&bpmp_clks TEGRA194_CLK_SDMMC_LEGACY_TM>;
clock-names = “sdmmc”, “pll_p”, “pll_c4_muxed”, “sdmmc_legacy_tm”;
uhs-mask = <0x08>;
nvidia,en-periodic-calib;
status = “disabled”;
};

WayneWWW · July 8, 2020, 6:18am

Hi,

I think you could just compare the property name and tell us what you are lacking of.
I don’t want you to get confused by the whole tx2 dts because the clk and pin info are all different.

gaozejun · July 8, 2020, 6:28am

I lack these below ,

force-non-removable-rescan;
vqmmc-supply
keep-power-in-suspend;
tap-delay
trim-delay
ddr-clk-limit
ddr-trim-delay

WayneWWW · July 8, 2020, 6:46am

Hi,

please add force-non-removable-rescan and keep-power-in-suspend directly.

and share us the dmesg and final dts file as attachment.

Thanks.

gaozejun · July 8, 2020, 12:14pm

Hi,
FInal dts file:

sdmmc1: sdhci@3400000 {
	compatible = "nvidia,tegra194-sdhci";
	reg = <0x0 0x3400000 0x0 0x00020000>;
	interrupts = < 0 TEGRA194_IRQ_SDMMC1 0x04>;
	iommus = <&smmu TEGRA_SID_SDMMC1A>;
	dma-coherent;
	max-clk-limit = <208000000>;
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	nvidia,vqmmc-always-on;
	cd-inverted;
	nvidia,min-tap-delay = <96>;
	nvidia,max-tap-delay = <139>;
	pwrdet-support;
	pinctrl-names = "sdmmc_e_33v_enable", "sdmmc_e_33v_disable";
	pinctrl-0 = <&sdmmc1_e_33V_enable>;
	pinctrl-1 = <&sdmmc1_e_33V_disable>;
	ignore-pm-notify;
	resets = <&bpmp_resets TEGRA194_RESET_SDMMC1>;
	reset-names = "sdhci";
	pll_source = "pll_p", "pll_c4_muxed";
	nvidia,set-parent-clk;
	nvidia,parent_clk_list = "pll_p", "pll_p", "pll_p", "pll_p", "pll_p", "pll_c4_muxed", "pll_c4_muxed", "pll_c4_muxed", "pll_c4_muxed", "pll_c4_muxed", "NULL";
	clocks = <&bpmp_clks TEGRA194_CLK_SDMMC1>,
		<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>,
		<&bpmp_clks TEGRA194_CLK_PLLC4_MUXED>,
		<&bpmp_clks TEGRA194_CLK_SDMMC_LEGACY_TM>;
	clock-names = "sdmmc", "pll_p", "pll_c4_muxed", "sdmmc_legacy_tm";
	uhs-mask = <0x08>;
	nvidia,en-periodic-calib;
	status = "disabled";
 };

sdhci@3400000 {
	mmc-ocr-mask = <0x0>;
	cd-gpios = <&tegra_main_gpio TEGRA194_MAIN_GPIO(G, 7) 0>;
	nvidia,cd-wakeup-capable;
    force-non-removable-rescan;
    keep-power-in-suspend;
	nvidia,vmmc-always-on;
    compad-vref-3v3 = <0x7>;
	compad-vref-1v8 = <0x7>;
    only-1-8-v;
	status = "okay";
};

And appendix is the dmesg log .log.txt (93.8 KB)

gaozejun · July 9, 2020, 1:41am

Hi,
SDIO still can not scan the wifi module(ap6398s).Please help me analys the log on #19.

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Does SDIO support wifi?

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