TX1 cannot successful disable SSC (Spread Spectrum Clocking) PEX_CLK0_P & PEX_CLK0_N.

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX1
1

Hi! Sir

We has tried Without https://devtalk.nvidia.com/default/topic/962847/?comment=4995007 #13
and With https://devtalk.nvidia.com/default/topic/962847/?comment=4995007 #13
The measured waveforms there are no difference between above two waveforms when disable SSC (Spread Spectrum Clocking) PEX_CLK0_P & PEX_CLK0_N on Jetson TX1 Developer Kit.

https://devtalk.nvidia.com/default/topic/962847/?comment=4995007 #13
drivers/platform/tegra/tegra21_clocks.c

#define USE_PLLE_SS 0

#if USE_PLLE_SS
val = clk_readl(PLLE_SS_CTRL);
val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
val &= ~PLLE_SS_COEFFICIENTS_MASK;
val |= PLLE_SS_COEFFICIENTS_VAL;
clk_writel(val, PLLE_SS_CTRL);
val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
pll_writel_delay(val, PLLE_SS_CTRL);
val &= ~PLLE_SS_CNTL_INTERP_RESET;
pll_writel_delay(val, PLLE_SS_CTRL);
#endif

include/linux/platform/tegra/clock.h

#ifdef CONFIG_ARCH_TEGRA_2x_SOC
#define USE_PLL_LOCK_BITS 0 /* Never use lock bits on Tegra2 /
#else
#define USE_PLL_LOCK_BITS 1 / Use lock bits for PLL stabiliation /
#define USE_PLLE_SS 0 / Use spread spectrum coefficients for PLLE /
#define PLL_PRE_LOCK_DELAY 2 / Delay 1st lock bit read after pll enabled /
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
#define PLL_POST_LOCK_DELAY 50 / Safety delay after lock is detected /
#else
#define USE_PLLE_SWCTL 0 / Use s/w controls for PLLE /
#define PLL_POST_LOCK_DELAY 10 / Safety delay after lock is detected */
#endif
#endif

SSC dis test_01 .docx (1.29 MB)

2

If it is R28.2, please use the following patch to disable spread.
To cross verify, please read back register value @ 0x60006068 address and make sure that bit-12 is set to ‘1’ to confirm SSC is disabled (busybox devmem 0x60006068 w)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 80ca8de05005..ff4365fd7e81 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -2252,7 +2252,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
     if (ret < 0)
         goto out;

-    if (pll->params->ssc_ctrl_reg != PLLE_SS_CTRL)
+    //if (pll->params->ssc_ctrl_reg != PLLE_SS_CTRL)
         goto out;

     val = pll_readl(PLLE_SS_CTRL, pll);
3

Hi! Vidyas

We tried following patch to disable spread.
And cross verify, read back register value @ 0x60006068 address and make sure that bit-12 is set to ‘1’ to confirm SSC is disabled (busybox devmem 0x60006068 w) as below
[0x00005C00]
Result: no difference after following patch to disable spread to disable SSC (Spread Spectrum Clocking) PEX_CLK0_P & PEX_CLK0_N on Jetson TX1 Developer Kit.

4

No difference as in when you connected scope and checked REFCLK waveform, you didn’t find any difference? i.e. even with 0x5C00 you still see spread enabled for REFCLK??

5

Hi! Vidyas

No difference when connected scope and checked REFCLK waveform, and I also ckeck again with 0x5C00 still see spread enabled for REFCLK.

6

Hi,
We tried with the same patch as #2 on our end and we could see that spread getting enabled/disabled.
Please find the attached waveforms
Spread Enabled
External Media
Spread Disabled
External Media

When spread is enabled, mean is around 4K+ ppm whereas in the spread disabled case, it is 50+ ppm
Can you please describe how you are measuring spread enable/disable?