Orin AGX SRNS clocking

Dear NVIDIA team,

We are working on a carrier board design with two Orin AGX SOMs within the same board. The two SOMs will be connected via a PCIe interface wherein one SOM shall act as RP and the other SOM will be EP. I came across the below note in the design guide and wished to seek clarification on the same.

  1. My inference from the above note is that we would need to connect an HCSL-compatible 100MHz oscillator output(without SSC) to UPHY_REFCLK0_N/P (at endpoint only) and PEX_CLK5_N/P (at Root port and Endpoint) shall be left open. Is this correct?

If so, Does NVIDIA have any recommended parts for the oscillator?

  1. “Clock output from Root Port is only recommended as backup option”

Would there be any issues if the clock output from the root port is connected as a ref clock? (instead of using a dedicated SRNS oscillator-based clock) Why is this stated as a “backup option”?
Note that in our application, PCIe signals will only be routed via PCB and no cables are involved.

We believe the Orin AGX developer kit uses a similar scheme. We referred to the developer kit schematics (A04) and noted that the PCIe connector sub-section consists of a mux chip for RP/EP operation. When two AGX Orin developer kits are connected (PCIe to PCIe), one side will be RP and the other side will be configured as EP which will control the mux to route the reference clock from RP to UPHY_REF_CLK pins of EP.

Looking forward to your reply.

Can we get a reply on this, please?

@Trumany, Could you please help us with this query?


As said, SRNS is recommended as each SoC should supply it’s own clock internally for accuracy. Clock from RP can be as backup if SRNS clock can not be achieved. The switch on devkit board is for general external RP/EP device, not for two Orin only.

Hello, @Trumany, I have a similar setup to the OP. What I am missing is how to enable SRNS on the SOM for a particular EP. Is this a BIOS setting or a device tree change?

We have tried modifying this setting in the device tree for the specific endpoint:

However, so far it is not working.


Please check this post. Will add this to document.

Hi @Trumany /@WayneWWW ,

Apart from the PCIe to PCIe connection between the SOM, two more PCIe devices(PCIe to Ethernet) are connected to the other PCIe root ports.

The below image shows the simplified PCIe Wake signal connection in our system.

The wake signals of the endpoint devices (PCIe to Ethernet chip) are connected to the wake pin of the SOM. As the wake pin of endpoint SOM is defined as output, we are not sure if the below connection is appropriate (Wake signal from PCIe to Ethernet chip will not be received by SOM). Could you please let us know about this?

Also, Is the wake pin open drain when the SOM is used as the end point?

SRNS Clocking strongly recommended. Each SoC should supply its own clock internally. Clock output from Root Port is only recommended as backup option."

After reading some of the other posts, I wanted to re-clarify my understanding of this statement. Is this clock source already available inside SoC? If so, Can I leave the PEX_CLK5_N/P and UPHY_REFCLK0_N/P open if I don’t intend to provide the aforementioned backup option in our system?

  1. As said in DG: PEX Wake: Unused for interfaces configured as Endpoint.
  2. Yes, the pins can be left unconnected.

Dear @Trumany ,

DG also mentions connecting the wake pins as mentioned below (page 52). The signal direction is indicated as output for endpoint. Could you please clarify this?


It is output from Endpoint to Root Port.

Dear @Trumany ,

We have connected the Wake signals of both SOMs according to the table that I shared in my previous comment.

As you mention that Wake PIN is un-used as an endpoint, is this connection unnecessary?

It is unuseful for EP, but need to connect to RP as a wake signal from EP to RP.

Dear @Trumany ,

Is the wake pin configured as opendrain when used as an endpoint?

It is always OD.

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