Hi,
Please check this post. Will add this to document.
| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
| Proper SRNS PCIe implementation Jetson AGX Orin | 4 | 340 | November 15, 2024 | |
| Orin AGX 100MHz PCIe reference clock | 8 | 511 | April 12, 2024 | |
| PCI Express EP Mode PWRDOWN_ERR on AGX Orin | 27 | 525 | March 7, 2025 | |
| SRNS for Jetson Orin AGX on Rel 36.3 | 2 | 91 | June 5, 2025 | |
| How to disable Orin PCIe common Refclk and enable separate refclk (SRIS/SRNS) | 17 | 2023 | August 29, 2023 | |
| Interfacing AGX Orin endpoint to an x86 PC using SRNS clocking | 2 | 389 | June 19, 2024 | |
| AGX Orin developer kit PCIe clock reference output | 2 | 472 | October 25, 2023 | |
| How to disable Orin PCIe common Refclk and enable separate refclk(SRIS/SRNS) | 3 | 757 | September 1, 2023 | |
| AGX Xavier PCIe SRNS (Separate reference clocks without SSC) | 3 | 416 | February 7, 2024 | |
| Use SRNS on CN4 Orin NX | 5 | 206 | November 5, 2024 |