Dear team,
We are Configuring the PCIe0 x4 as a Root Complex, so it will generate the PCIe Clock, and it is going to End point.
If we want to use this as end point configuration, how we need to give the Clock to the PCIe0 Clock pins. How we need to configure as an end point.
Please provide the solution.
If this is for hardware design part, “Jetson AGX Xavier Series PCIe Endpoint Design Guidelines Application Note” in below link might help. The design for this part is generic for Orin and Xavier.