Jetson AGX Xavier PCIe Reference Clk signal level too low

The measurement shows that the 100MHz PCIe Ref Clock from Xavier module has amplitude of 300mV single ended or 600mV pk2pk without termination. With 50 Ohm (100 Ohm differential) internal FPGA termination, the amplitude is reduced down to 150mV S.E. or 300mVpp diff.
The problem is the FPGA has 250mVpp min. spec, which left us 50mVpp margin.

The normal PCIe standard HSCL driver provides upto 1500 mVpp, how come the Xavier only outputs 600mVpp? One key spec I am looking for is what is the guaranteed output range. What is the minimum output peak to peak voltage from Xavier?

Hello,

Welcome to the NVIDIA Developer forums! Your topic will be best served in the Jetson category.

I will move this post over for visibility.

Cheers,
Tom

You can refer to this topic: Regarding PCIE clock of Jetson TX2 - #4 by vidyas

Hi Trumany, I am not sure if your referred link addresses my questions.

  1. After reviewing the Technical Reference Manual for the Xavier, I did not find any information pertaining to the PCIe reference clock setting registers that are documented in the TX2 Technical Reference Manual. Could you please clarify whether the PCIe circuit design and register configurations related to the reference clock are identical between the TX2 and Xavier platforms, or if there are any differences?

  2. In our configuration with the Xavier, we are measuring differential PCIe signals around 300mVpp, which is near the minimum specified by the PCIe standard. At times, the signal drops below 300mVpp to around 290mVpp, which violates the specification. Our setup includes a 100 ohm termination on the endpoint FPGA side, which cannot be disabled. Given that most endpoints have this termination enabled, how does the Xavier still claim compliance with the PCIe standard’s 300mVpp minimum requirement?

  3. To assist us in designing with the Xavier, could you please provide the equivalent circuit diagram for the PCIe reference clock, as well as the relevant configuration register setting manual?

  4. Based on forum discussions about the TX2, there appear to be two types of termination resistances: the driver common mode resistance (22 to 38 ohms) and the driver resistance (43 to 52 ohms). Could you please provide a diagram illustrating these two types of terminations? Additionally, there is a parameter called IBIAS current (50uA to 300uA). Could you describe how this parameter helps in tuning the PCIe reference clock?

  5. The output driver current (4mA to 16mA) seems to be a critical parameter for us. Currently, we are observing around 300mV (single ended) on the Xavier when there is no termination, suggesting an output driver current of approximately 6mA. If this is the case, it would fail to meet the PCIe standard. Could you please provide detailed guidance on how to boost the output driver current to 15mA or higher on the Xavier platform to ensure compliance with the PCIe specification?

Thanks

Hi, please share which REFCLK pins are you testing with? How did you do the measuement? Is it on devkit or custom board?

PCIe tuning is not supported as you can see in the Tuning Guide doc, as custom design is expected to follow DG routing requirements well and the default amplitude value is max amplitude.

The measurement was done on both devkit (Xavier with Xilinx KCU105 kit), and our own product board. Particularly, I am using PEX_CLK5_P/N (F24/25) pin.

If this is the maximum signal level, a lot of endpoint products interfacing Xavier will fail to meet PCIe spec.

Could you please share the scope waveform?

Did you configure the clock switch to PEX_CLK5 as below? If not, it would be NVHS_SLVS_CLK.

Hi Truman, please focus on my original questions. Nvidia should disclose the spec and expected behavior of the PCIe reference clock, which l have not seen or found.

We have been using Xavier as the root complex, and configuring it to provide the reference clock. So the mux is set to use PEX_CLK5.

We measure the signal using high bandwidth differential probe. Here’s a captured image.

Again, a robust design should provide 600 to 700mV peak to peak voltage. At least 450mV to claim meeting PCIe 300mV standard.

Did you probe the GPIO6 voltage level to make sure it is low during test?

I will check the GPIO6 level and let you know. In the same time, please assume it is low, because FPGA receives the 100Mhz clock from Xavier. Also, our custom board does not have the mux and uses the PEX_CLK5 directly. The measurement results are the same. So the problem is not related to the mux or the other clock.

Could you please check with your experts what signal level we should expect to see when there is 100 ohm differential termination on the endpoint?

I measured the GPIO6 signal and it is 0 volt. Any progress on your side?

We are checking this internally. But at least, the output of REFCLK (600mV swing) is in the range of REFCLK spec and your device termination should be removed.

Hi Trumany,

We are using AMD/Xilinx Kintex Ultrascale FPGA. It does not provide any option to remove the internal 100 Ohm termination. I am not sure whether other FPGAs provide the flexibility. Regardless, let’s focus on the Xavier side. Could you please provide an equivalent circuit and specify the common mode voltage range, differential voltage range, and source termination resistance range?

Below are two equivalent diagrams I can think of with some typical numbers. Please provide something like this.

We don’t provide that. As said, the output is in the range of spec. According to previous guide, from Xavier, PCIe tuning is not allowed as custom design is expected to follow Design Guide well. We are checking if it is possible/allowed to tune the strength internally.

Any progress from Nvidia?
In terms of the range of spec, I am not aware of the document showing the number of the signal level and termination requirement. Could you please point me to that document?

Would a PCIe clock buffer between Jetson and FPGA help?

It depends. If the end termination (100 Ohm differential) is used at the input to the Si53102, Xavier won’t meet VIHmin = 150mV spec of Si53102. In this case, Si53102 is even worse than Xilinx FPGA, where VIHmin = 125mV.

If no end termination is used, Xavier should be OK based on our measurement, but we need to see the spec from Nvidia, including the range of the signal level and source termination value.

It is confirmed that PCIe tuning is not supported. PCIe REFCLK measurements (including amplitude) should be done without any termination. We have no other spec than below PCIe REFCLK spec.