We are having trouble with 4-lane PCIe links on our custom PCB between the AGX Xavier and PCIe switch training at Gen3 speed. Gen2 speed is successful when the switch is configured to do so, but attempts to configure for Gen3 speed result in the LTSSM dropping down to Gen1 speed. There do not appear to be any problems with the lanes, as all 4 lanes are properly read by the PCIe switch and the Jetson registers. Attempts to fix this problem by disabling ASPM and making edits to the PCI driver sources have not been successful to link train at Gen3.
The TX2 tuning guide contains registers for controlling PCIe REFCLK current and resistance values, as shown in this post: Regarding PCIE clock of Jetson TX2 - #15 by Trumany. However, this information is not contained in the AGX Xavier tuning guide or TRM documents. Do equivalent registers exist for the AGX Xavier to control PCIe PEX_CLK5?
This may be an emphasis / de-emphasis problem, as the issue exists at the physical layer. Probing the TX lines between the Xavier and the PCIe switch results in an eye diagram that “jumps” two two distinct high and two distinct low levels instead of just one distinct high and low.
I have not flashed the Xavier with the modification to pcie-tegra.c yet for testing. However, I am curious at this point the full range of deemphasis levels that are available for PCIE_CAP_COMPLIANCE_PRESET in the PCIE_X4_RC_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_0 register. The TRM does not go into detail, but since PCIE_CAP_COMPLIANCE_PRESET has four bits (15:12), there could be additional settings beyond -6.0 dB (0000b) and -3.5 dB (0001b).
Is there a description available of the PCIE_CAP_COMPLIANCE_PRESET settings?
