Jetson TX1/TX2 PCIE differential reference clock type


Is TX1/TX2 PCIE differential reference clock HCSL or LVDS?


Hi, it’s HCSL.

If the PCie REFCLK is HCSL-based it must be terminated either at the source or at the receiver end.

Since some PCIe slot may not be fitted it is generally preferable to terminate at the source.

*****Could you please confirm that the termination scheme (typically Rs=33R + 50R to ground) for the PCIe REFCLK is present as a source termination scheme WITHIN the TX2 module ? ********

Section 5.2 of the TX2 OEM Design Guideline does not show those being present but I imagine that they must exist which is why on the reference schematic has no external receiver termination scheme showing.

Thank you.

Could it be that the TX2 drivers are all of the LP-HCSL (low power) type and not so much traditional HCSL type.

AN879 from I.D.T is very useful on the matter.

LP-HCSL type would mean that no termination resistor to ground are needed and allows for series AC coupling capacitors between driver and receiver.

It would also mean that LP-HCSL can drive double terminations where a receiver integrates a 100ohms differential resistor in the chip. Those typically require AC coupling of the clock signals.

AC coupling capacitors is required by the device that I am trying to attach to: Pericom PI7C9X2G404SL

Dataheet: “3. In general rule, use ac-coupling when differential input >500mV; use dc-coupling when differential input <400mV, such as LVDS drive with 100 ohm across at the inputs”

Also ,there are no OEM design guidelines related to the REFCLK outputs . I imagine that the pairs want to be 100ohms differential as opposed to 85ohms differential ?

Please confirm.

Thank you.

PCIe interface is compliant to the PCIE CEM specification. You can refer to the spec for details.

Your reply seems to be a little rush~
Please note that PCIE CEM specification alone can not decide how the REFCLK± are terminated.
PCIE CEM only says “The nominal single-ended swing for each clock is 0 to 0.7 V and a nominal frequency of 100 MHz ±300 PPM”, which has nothing to do with the resistor termination policy of the differential clock pins themself.

I wish to comfirm the following two things:

  1. Do REFCLK± pins conform to HCSL electrical standards ? (i can’t see any useful info regarding this, neither DS nor OEM Design Guide). Otherwise please point out to what electrical standard shall REFCLK± conform?

  2. Please show how REFCLK± pins are terminated on the TX2 module (if any). Or are these two pins simply not terminated at all ?