PCIe ref clock source termination

We are currently designing a dual TX2 platform. I am looking over the PCIe connections and I have a question about termination on the PCIe ref clock.

PCIe spec calls for a source termination network close to the driver. I do not see this on the carrier board schematics nor in the Tx2 hardware design guide.

Are these termination resistors built into the Jetson module?

Thanks, JB.

I would really appreciate it of someone could get back to me on this.

Thanks and regards,

We will check this and get back to you

Can someone get back to me on this please?

Hello John,

I am looking for a technical resource to assist.

Thanks for your patience,

Hi John,

The engineer is working on this now. He is awaiting information from the development team.
Please hang tight.

Thanks for your patience.


Hi, the termination is built in pad.

Common mode termination resistance is enabled in Tegra itself (hence you don’t see it on the board)

Hello everyone,
That’s great. Thanks for the clarification on this.