I have connected to the Jetson TX2 development kit a PCIe card with 4 serial RS-485 ports, based on chip EXAR XR17V354. The board is properly detected by the kernel as per lspci command: 01:00.0 Serial controller: Exar Corp. Device 0354 (rev 03) (prog-if 02 [16550]) Control: I/O- Mem+ BusMaster- …

Nvidia Tegra (till TX2) doesn’t support true DW (Double Word) unaligned accesses. It always sends a request for 4 bytes (i.e. DW aligned address) and then uses ‘byte enable’ concept to return only the data that CPU is really looking for. So, in this case, the 32-bit read is auto clearing the bits, …

Which interrupt is enabled by the device driver for this device? Is it Legacy or MSI-X? (Because I already see MSI is not enabled) Also, what is the procedure being followed here to force edge interrupts?

Thanks vidyas for the quick reply. How to distinguish between legacy and msi irq? The driver uses request_irq();

01:00.0 Serial controller: Exar Corp. Device 0354 (rev 03) (prog-if 02 [16550]) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- SERR- <PERR- INTx- Interrupt: pin A routed …

don’t you see any MSI specific code in the driver like pci_enable_msi()? Also, I don’t see “BusMaster+” instead see “BusMaster-”. Without enabling Bus mastering capability of the device, how is the device able to do DMA to/from the system? Is this device driver ‘xrserial’ an upstream driver? (I d…

The driver is provided by the chip manufacturer. I don’t think DMA is needed since everything works with interrupts either for writing data into FIFOs or reading from. I just see pci_enable_device(dev) but no mention about pci_enable_msi(). I see on few NVidia drivers pci_enable_msi(). Should I …

Hi vidyas, I did what you recommended and I discovered that the issue isn’t related to interrupts but, probably to memory transactions on the bus. Here is the sequence of states compared between Intel x86 and NVidia TX2. On Exar chip I have 2 addresses where I can read the interrupt register of t…

Is there any feedback about if it is possibile to read PCIe at 8, 16 and 32 bits ? I suppose this is the main issue.

PCIE spurious interrupts

Robotics & Edge Computing Jetson Systems Jetson TX2

vidyas March 20, 2020, 6:01am 4

Also, why is BusMaster not enabled for this device? Can you please attach ‘sudo lspci -vv’ after device driver is bound to the device?

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PCIE spurious interrupts

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