Probing the OSC signal using DSO - AGX Orin

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Orin
,
1

Hi,

We are using Jetson AGX Orin development Kit and we are generating the trigger pulse for the camera using TSC signal generator at 30 Hz. We are able to get the trigger pulses at 30 Hz at the configured pin.

We are evaluating the jitter in trigger pulse, and we need to probe the parent clock source of 30 Hz trigger pulse to measure the jitter of the PWM signal from its original clock source.

We are able to find the parent clock source of the trigger pulse which is OSC. (tsc_ref (31.25 MHz) → tsc (38.4 MHz) → OSC(38.4 MHz) ). Could you please confirm whether this is correct?

We need to probe the OSC signal in Oscilloscope and for that we need to map the OSC signal to some IO. Could you please let us know the procedure to do this or any other way to probe the OSC signal?

Regards,
Arun

4

Hi, which pin did you use to generate 30Hz clock? You can refer to the Orin TRM doc for more info. https://developer.nvidia.com/downloads/orin-series-soc-technical-reference-manual/

5

Hi Trumany,

Thanks for the quick reply.

We are using the CAM_FRSYNC1 (A62) pin for generating 30 Hz pulse. Please find the DTB entry below.

tsc_sig_gen@c6a0000 {
        compatible = "nvidia,tegra234-cdi-tsc";
        ranges = <0x0 0x0 0xc6a0000 0x10000>;
        reg = <0x0 0xc6a0000 0x0 0x18>;
        #address-cells = <1>;
        #size-cells = <1>;
        status = "okay";
            /* EDGE_OUT #0 */
            generator@380 {
                reg = <0x380 0x80>;
                freq_hz = <30>;
                duty_cycle = <25>;
                offset_ms = <0>;
                status = "okay";
                };
            /* EDGE_OUT #1 */
            /*generator@400 {
                reg = <0x400 0x80>;
                freq_hz = <20>;
                duty_cycle = <25>;
                offset_ms = <0>;
                status = "disabled";
            };*/
            /* EDGE_OUT #2 */
            /*generator@480 {
                reg = <0x480 0x80>;
                freq_hz = <20>;
                duty_cycle = <25>;
                offset_ms = <0>;
                status = "okay";
            };*/
            /* EDGE_OUT #3 */
            /*generator@500 {
                reg = <0x500 0x80>;
                freq_hz = <20>;
                duty_cycle = <25>;
                offset_ms = <0>;
                status = "okay";
            };*/
        };

We have traced the parent clock of 30 Hz trigger pulse using the below steps.

  1. From the DTB entry, “tegra234-cdi-tsc” driver is used for trigger pulse generation.
  2. From the driver source of “tegra234-cdi-tsc”, “tsc_ref” clock is used as reference clock for pulse generation.
  3. From the command “cat /sys/kernel/debug/bpmp/debug/clk/tsc_ref/rate”, the rate of tsc_ref clock is 31.25 MHz.
  4. From the command “cat /sys/kernel/debug/bpmp/debug/clk/tsc_ref/parent”, the parent of tsc_ref is “tsc”.
  5. From the command "cat /sys/kernel/debug/bpmp/debug/clk/tsc/parent’, the parent of tsc is “osc”.
  6. From the command "cat /sys/kernel/debug/bpmp/debug/clk/osc/rate ", the rate of osc is 38.4 MHz.

From the above steps, OSC is the source clock for 30 Hz generation. To evaluate and measure the jitter in trigger pulse, we need to probe the OSC signal. Please let us know a way to probe the OSC signal.

Thanks & Regards,
Arun

6

Hi Team,

Any update on the above query?

Thanks & Regards,
Arun

8

Hi, the OSC is not routed out, you can’t probe it outside. The p/n of it is AY38460301, maybe you can find useful info accordingly.

10

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.