Question about Tesla L4 performance vs RTX A4500 with lower memory bandwidth

[tkdals7240]

Hello,

I have a question after comparing RTX A4500 (Ampere) and Tesla L4 (Ada Lovelace).

On paper, Tesla L4 has a much narrower memory bus (64-bit vs 320-bit) and significantly lower raw memory bandwidth/clock speed than RTX A4500.
However, in some benchmarks and real workloads, the performance appears to be similar or sometimes better, and I’m trying to understand why.

From what I understand, starting with Ada architecture:

• L2 cache size was significantly increased

• Memory access and compression algorithms were improved

• The architecture seems more focused on reducing DRAM traffic

My questions are:

1. Does Ada (L4) actually rely much less on DRAM compared to Ampere (A4500)?

2. How much do the larger L2 cache and improved memory compression impact real-world performance?

3. Despite the much narrower memory bus, what are the main architectural reasons that allow L4 to maintain similar performance?

If there are any official documents or technical blogs explaining this, I would really appreciate any references.

Thank you.

[Richard3D]

Is this hardware question related to NVIDIA OMNIVERSE? We don’t really answer generic hardware questions here, not related to issues with running Omniverse. However, I will answer it this time.

Ada Lovelace GPUs like the L4 can rival or beat an RTX A4500 in many workloads despite a much narrower memory bus because they waste far less bandwidth. A much larger, higher‑bandwidth L2 cache, better cache policies, and stronger on‑the‑fly compression dramatically cut DRAM traffic, sometimes by over half. When most data reuse happens in L2 and registers, the external bus matters less, so L4’s smaller bus is offset by high effective bandwidth. At the same time, newer tensor cores (with FP8, sparsity, and higher clocks) give L4 more compute per watt, letting it stay competitive even with lower raw GB/s.