Questions about communication between SPE and CPU complex

We are designing a product needed some GPIOs,PWM x 4,SPI x 1 and I2C x 1. We must figure out these interfaces. But so many processors in the Paker SoC make us difficult to code. Here we lists some questions about the communication between SPE and CPU complex.

(1) TX2 module has 8x50 pins, and is that a pin only connect to a special processor, or shared by processors? How can I figure out it?

(2) We know SPE runs FreeRTOS, and CCPLEX runs linux, how can they communication?

(3) Could SPE’s GPIO,SPI,I2C,PWM be used by Linux? For example, in factory, if we just need verify the HW, can we 1)easily operate the interfaces by Linux. 2)After upgrade to final FW, the interfaces turn to be operated by RTOS.

(4) From TECHNICAL REFERENCE MANUAL for the NVIDIA Parker Series SoC, Chapter 18.23: The AON cluster implements one PWM. That means SPE support one PWM controller(8 PWM output) or only support 1 PWM output?

Any help would be very appreciated.

Hello, garretzou:

  1. In current SDK (32.2), besides CCPLEX (Linux), SPE R5 (FreeRTOS) firmware source code is also public. Generally, SPE R5 is in AON cluster, and so all modules accessed by SPE should be within AON cluster. (Refer to TX2 TRM for details about AON and modules inside.) Also, all modules current supported in SPE firmware are listed in doc/, and you can check that.
  2. Refer to A sysfs node ‘data_channel’ shows an example to exchange messages between CCPLEX and SPE. Check code listed for details. Basically, the communication is implemented by HSP and shared memory.
  3. yes. CCPLEX can access those modules with correct settings. But please pay attention to configuration/access conflict if a module is configured/accessed by both CCPLEX and SPE R5.
  4. Only 1 PWM module in AON cluster.