Sensor Processing Engine (SPE) IVC communication with CCPLEX in Jetson TX2

I’m actually working on a project involving the SPE and the CCPLEX units of the Jetson TX2. I’ve referred to the “Jetson Sensor Processing Engine (SPE) Developer Guide” to build, run and flash the FreeRTOS based project without any problem. I’ve also successfully tested the IVC communication and everything seems to work as expected. But I’ve some questions about the process for learning purposes. My questions are:

  1. What does IVC stands for? (I couldn’t find this information in any of the Nvidia documents/guides).
  2. To properly run the GPIO example (Jetson Sensor Processing Engine (SPE) Developer Guide: GPIO Application (app/gpio-app.c)) we should prevent the Kernel from using the GPIO. Are the CCPLEX and SPE using the same GPIO peripheral? I thought that the SPE is an independent microcontroller with its own GPIO and other peripherals.
  3. What is the “GPIO SCR” ? What are we actually changing by modifying a scr.X value in a .cfg file
  4. Why do we have the modify the PADCTL register of the pinmux? What is the pinmux used for in the Jetson TX2 SoC?
  5. I know that we can use some printf’s to debug the SPE binary, but is it possible to use an IDE to debug the code line by line using the spe.elf file? If yes which IDE would you suggest?

Any detailed answer will be highly appreciated. I couldn’t find/see suitable answers for these questions in the online available materials.

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  1. IVC – Inter-VM Communications
  2. Those modules, like GPIO, CCPLEX, SPE (in AON cluster), etc., are all inside the Tegra SOC. You can check the system block diagram in TX2 TRM for details. Some GPIOs are in AON cluster, but CCPLEX can also access them. And SPE (in AON cluster) can also access those modules outside of AON cluster, as long as the configurations are correct.
  3. SCR is security control register. yes, please follow the doc for configuration updating.
  4. Some pins are multi-purpose pins. pinmux is to configure which purpose of that pin, and some other pin properties. Refer to corresponding register description in TX2 TRM for details.
  5. I have not tried in TX2. No official support for that feature yet.


Thanks for your prompt reply. How reliable is the the IVC communication comparing to other protocols such as UART, CAN, …? Did you do any performance analysis concerning the IVC? Does the VM stands for Virtual Machine (using VSOCK socket)? If yes what’s the relation between virtual machines with the Jetson TX2 modules?

IVC is based on shared-memory, so it should be more reliable and efficient.
Current implementation in Linux side is based on mbox, and message size is 64-byte. I have not test the performance yet. But depending on use case, it should be flexible to improve.
Don’t bother with name (VM), and basically, you can treat that (IVC) as a mechanism which exchanges data between different entities, like CCPLEX and SPE.


Is there any possible way to access the emmc from the spe fw? I need to save some data in a non-volatile memory.

No, please send message to CCPLEX for that goal.


What is the /sys/devices/aondbg used for? Can I use it to debug the SPE unit ? If yes how?

That’s not for SPE debug.
The simple way is still to add some print code in SPE firmware to debug.