hi：
one max9296 corresponds to two max9295，We have verified that the sensor is ok，
Now replace the sensor with an fpga to generate the signal，test one chansel ok，two cnansel is not ok
Both of them working individually??
Thanks
So it without problem to open camera 1 and camera 2 but failed open two simultaneously, right.
Orin able to support the case without problem you can reference to imx390 for reference.
…/hardware/nvidia/platform/t23x/common/kernel-dts/t234-common-modules/tegra234-camera-imx390-a00.dtsi
hi:
dts should be fine, now connecting two sensors is fine
upload the dts，please check
sgx-yuv-gmsl2.dtsi (56.4 KB)
Suppose the vc-id should start from 0 instead of 1.
Should be 0 and 1 instead of 1 and 2
tegra-capture-vi {
num-channels = <8>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
jetson_vi_in0: endpoint {
vc-id = <1>;
port-index = <0>;
bus-width = <4>;
remote-endpoint = <&jetson_csi_out0>;
};
};
port@1 {
reg = <1>;
jetson_vi_in1: endpoint {
vc-id = <2>;
port-index = <0>;
bus-width = <4>;
remote-endpoint = <&jetson_csi_out1>;
};
};
hi:
i have change it, but test is not ok,
upload the dts and trace log, please check.
sgx-yuv-gmsl2.dtsi (56.4 KB)
caijika-trace0718.log (4.9 MB)
Modify the serdes_pix_clk_hz and pix_clk_hz to 370000000
and boost the clocks to try.
sudo su
echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/isp/rate
cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate
cat /sys/kernel/debug/bpmp/debug/clk/emc/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/emc/rate
hi:
Modify the serdes_pix_clk_hz and pix_clk_hz to 370000000----> have change it,test is not ok
serdes_pix_clk_hz —> max926 0x320 reg set 0x2e,
upload the trace log and dts
caijika-trace0719.log (2.1 MB)
sgx-yuv-gmsl2.dtsi (56.4 KB)
Does the sensor output embedded data ?
Modify the embedded_metadata_height in dts if yes
hi:
the fpga generate signal without embedded data.
Could you get the trace log for launching single camera to check. Please get both of them.
Thanks
hi：
Modify the serdes_pix_clk_hz and pix_clk_hz to 370000000------>
i change serdes_pix_clk_hz to 600000000，and pix_clk_hz change to 370000000 or 320000000, test is ok, now i see the kernel driver find the pix_clk_hz is not use,
code
drivers/media/platform/tegra/camera/csi/csi.c
if (sig_props->serdes_pixel_clock.val != 0ULL)
332 pix_clk_hz = sig_props->serdes_pixel_clock.val;
333 else
334 pix_clk_hz = sig_props->pixel_clock.val;
335 deskew_enable = sig_props->deskew_initial_enable;
336
337 if (pix_clk_hz >= CLK_HZ_FOR_DESKEW && deskew_enable) {
hi：
any update？
Didn’t you check sensor driver and gmsl driver have any configure depend on pix_clk_hz?
And how did you boost the clocks?
hi：
Didn’t you check sensor driver and gmsl driver have any configure depend on pix_clk_hz?
i can see the code
And how did you boost the clocks?-----》change the serdes_pix_clk_hz to 600000000, set max9296
0x320 set to 2.4G
Please boost the clocks by below command.
sudo su
echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/isp/rate
cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate
cat /sys/kernel/debug/bpmp/debug/clk/emc/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/emc/rate