Regarding SPI MOSI/ MISO voltage levels in Jetson Nano

Autonomous Machines Jetson & Embedded Systems Jetson Nano
1

Hello support,

We are using our carrier board having Jetson Nano. We have level translator NTS0101PW to interface SPI devices at 3.3V. However, we found SPI MOSI & MISO signal levels settle to ~1.5V from 1.8V at rising edges of data. Please find attached waveforms. No such behavior in clock/ CS signal.

We are using 2 SPI, SPI0 & SPI, in both MOSI/ MISO settle to ~1.5V. To troubleshoot we lifted MISO of translator pin on 1.8V (Jetson side) & found signal was 1.8V on lifted pin. So issue appears after connecting to Jetson pins. Not sure why such behavior from Jetson side.

Apart from this, similar level translator is used in I2C & UART but voltage levels in other peripherals seems to be OK. Please advise ahead.

Regards,
jagdish
SPI0.rar (28.4 KB)
SPI1.rar (29.2 KB)

4

Hi, can you see same behavior on your devkit? There are level shift on devkit too, if can’t be repro on devkit, then it looks more like the level shift issue.

5

Hi, there are other low & high frequency signals, UART, I2C which don’t show this issue & all using same level translator. It is only SPI MOSI & MISO signals (not even CLK & CS). Do you still think issue lies with level translator?

7

@jagdish.karamchandani
Did you configure the SPI pin by jetson-io?

8

Hello,
We have configured SPI by device tree file & not by Jetson IO.

9

What’s the REG by below command.

sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
10

Hello,

Please find attached response to the said command.
NVIDIA response.docx (11.7 KB)

11

Looks like the REG without problem.
Could you check the GPIO again.

sudo cat /sys/kernel/debug/tegra_gpio

sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
Bank: 1 Reg: 0x70003050 Val: 0x0000e044 -> spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e044 -> spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e044 -> spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e048 -> spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e048 -> spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006044 -> spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006044 -> spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006044 -> spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006044 -> spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006044 -> spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e015 -> spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e015 -> spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e015 -> spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e015 -> spi4_cs0_pc6
12

Hello,
We took waveforms in Jetson Nano eval kit on 1.8V side for SPI0_MISO & results are same as our carrier board, i.e MISO line dips to 1.5V after peaking to 1.8V. However, there is no such behavior in clock/ CS signal of eval board which again is similar to our carrier board. Waveform attached.
Kindly advise further.

SPI0 _MISO.bmp (1.8 MB)

16

Did you configure the pin by jetson-io for devkit? Any device tree modification?

Could you use jetson-io to configure those pin with original system image without modification to check if device tree configure cause the problem.

Thanks

17

Hello,

We see no change after using original system image & using Jetson-IO to configure, i.e we see distortion. Please see attached image for more clarity. Kindly advise further.

SPI0 _ MISO_11 Mar 22 (3).bmp (1.8 MB)
SPI0 _ MISO_11 Mar 22 (2).bmp (1.8 MB)

18

Could you dump the REG and GPIO pin to check.

sudo cat /sys/kernel/debug/tegra_gpio

sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
Bank: 1 Reg: 0x70003050 Val: 0x0000e044 -> spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e044 -> spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e044 -> spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e048 -> spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e048 -> spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006044 -> spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006044 -> spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006044 -> spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006044 -> spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006044 -> spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e015 -> spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e015 -> spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e015 -> spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e015 -> spi4_cs0_pc6
19

Below response for the command you suggested,

cat /sys/kernel/debug/tegra_gpio

Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
A: 0:0 64 40 40 04 00 00 000000
B: 0:1 00 00 00 00 00 00 000000
C: 0:2 00 00 00 00 00 00 000000
D: 0:3 00 00 00 00 00 00 000000
E: 1:0 00 00 00 00 00 00 000000
F: 1:1 00 00 00 00 00 00 000000
G: 1:2 00 00 00 00 00 00 000000
H: 1:3 fd d9 40 60 00 00 000000
I: 2:0 07 03 03 02 00 04 000404
J: 2:1 00 00 00 00 00 00 000000
K: 2:2 00 00 00 00 00 00 000000
L: 2:3 00 00 00 00 00 00 000000
M: 3:0 00 00 00 00 00 00 000000
N: 3:1 00 00 00 00 00 00 000000
O: 3:2 00 00 00 00 00 00 000000
P: 3:3 00 00 00 00 00 00 000000
Q: 4:0 00 00 00 00 00 00 000000
R: 4:1 00 00 00 00 00 00 000000
S: 4:2 a1 a1 01 00 00 00 000000
T: 4:3 01 01 00 00 00 00 000000
U: 5:0 00 00 00 00 00 00 000000
V: 5:1 02 00 00 02 00 00 000000
W: 5:2 00 00 00 00 00 00 000000
X: 5:3 78 08 08 70 00 60 606000
Y: 6:0 02 00 00 02 00 00 000000
Z: 6:1 0e 08 08 04 00 06 020600
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 00 00 00 00 00 00 000000
CC: 7:0 92 80 80 02 00 12 121200
DD: 7:1 00 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000
cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
Bank: 1 Reg: 0x70003050 Val: 0x0000e044 → spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e044 → spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e044 → spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e048 → spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e048 → spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006044 → spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006044 → spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006044 → spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006048 → spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006048 → spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e015 → spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e015 → spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e015 → spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e015 → spi4_cs0_pc6
Bank: 1 Reg: 0x70003088 Val: 0x00002040 → qspi_sck_pee0
Bank: 1 Reg: 0x7000308c Val: 0x00002000 → qspi_cs_n_pee1
Bank: 1 Reg: 0x70003090 Val: 0x00002040 → qspi_io0_pee2
Bank: 1 Reg: 0x70003094 Val: 0x00002040 → qspi_io1_pee3
Bank: 1 Reg: 0x70003098 Val: 0x00002040 → qspi_io2_pee4
Bank: 1 Reg: 0x7000309c Val: 0x00002040 → qspi_io3_pee5
Bank: 0 Reg: 0x70000b70 Val: 0x00000001 → drive_qspi_comp_control
Bank: 0 Reg: 0x70000b78 Val: 0x00000001 → drive_qspi_lpbk_control
Bank: 0 Reg: 0x70000a78 Val: 0x00808000 → drive_qspi_comp

20

The configure without problem.
Could you try loopback test for the functionality.

https://forums.developer.nvidia.com/t/155310/2

21

Shane–Could you let us know on what you are doubting, do you intend to change the slave device? Do you have source/ sink current capacities of IO in your mind creating issues? I will try loop back but can we try replacing slave device if it looks comfortable to you?

22

Current I only able to verify the SPI functionality by loopback test.
I need time to arrange resource to probe to confirm the problem.

Also what do you mean replacing slave devices?

23

I mean hooking different SPI device instead of one that we are using now. We can take out SPI bus & connect to some different SPI slave device.