Why the voltage of SPI_1_CS0 (J41 Pin 24) alway lower than GND?

Autonomous Machines Jetson & Embedded Systems Jetson Nano
#1

Hi Guys,

After enable SPI1 by tegra-io utility in nano dev kit running on l4t32.3.1, I shortcut SPI_1_MOSI(J41 Pin 19) and SPI_1_MOSI(J41 Pin 21) and test by linux official spidev_test tool, it works.

sercomm:~$ sudo ./spidev_test -D /dev/spidev0.0 -v -p "test spi1"
spi mode: 0x0
bits per word: 8
max speed: 4000000 Hz (4000 KHz)
verbose=1
TX | 74 65 73 74 20 73 70 69 31 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  | test.spi1
RX | 74 65 73 74 20 73 70 69 31 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  | test.spi1

But when I test the Nano dev kit SPI1 with a slave(stm32 Nucleo), the voltage of SPI_1_CS0(J41 Pin 124) is about -1.9V, and more or less 0V same as that of GND after use the above script "sudo ./spidev_test -D /dev/spidev0.0 -v -p “test spi1”. The slave and master can’t communicate through spi1. As we all known, the CS pin of SPI1 should high or low when transfer data, that is so weird.

Jetson Nano GPIO setting LOW or HIGH problem
#2

Hi,
Signal to Jetson Nano devkit J41 pin 24 is SPI1_CS0_LS, this is a signal after level shifter.

The level shifter used is TXB0108RGYR, it’s designed to drive capacitive loads of up to 70 pF. The output drivers have low dc drive strength. If pullup or pulldown resistors are connected externally to the data I/Os, their values must be kept higher than 50 kΩ to ensure that they do not contend with the output drivers.

So please check if any strong pull on this pin when you use it, remove it should able to get a pure H or L logic.

#3

Hi Jim,

Thank you.

After shortcut MOSI and MISO, we get the waves(below pic.) of SPI_1_SCK and SPI_1_CS0 of Jetson Nano dev kit with L4t32.3.1 by a logic analyzer.
External Media

Seem the CLK is broken. How to make the SPI_1_SCK work normally?

We use the linux official spidev_test tool to test. We just need set a clock speed to the follow spi_ioc_transfer, and the clock should worked.

struct spi_ioc_transfer tr = {
        .tx_buf = (unsigned long)tx,
        .rx_buf = (unsigned long)rx,
        .len = len,
        .delay_usecs = delay,
        .speed_hz = speed,
        .bits_per_word = bits,
    };

The dts(tegra210-p3448-0000-p3449-0000-a02-user-custom.dts generated by tegra-io utility) of spi1 relative configuration is as below.

spi1_sck_pc2 {
                                nvidia,pins = "spi1_sck_pc2";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <0x1>;
                                nvidia,tristate = <0x1>;
                                nvidia,enable-input = <0x0>;
                        };

                        pin23 {
                                nvidia,enable-input = <0x1>;
                                nvidia,tristate = <0x0>;
                                nvidia,pull = <0x1>;
                                nvidia,pins = "spi1_sck_pc2";
                                nvidia,function = "spi1";
                        };

Thanks

#4

Hi,
SPI1_SCK_LS also signal after level shifter, please also check if any strong pull on this pin.

#5

Hi JimWang,

We do not add any other pull to any pins on the dev kit, just let it as factory default configuration.

Please take a second look at the revision #3

Thanks

#6

Could you check the GPIO group C status by below command.

sudo cat /sys/kernel/debug/tegra_gpio

#7

Hi ShaneCCC,

sercomm:~$ cat /sys/kernel/debug/tegra_gpio
cat: /sys/kernel/debug/tegra_gpio: Permission denied
sercomm:~$ sudo !!
sudo cat /sys/kernel/debug/tegra_gpio
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
 A: 0:0 64 40 40 04 00 00 000000
 B: 0:1 00 00 00 00 00 00 000000
 C: 0:2 00 00 00 00 00 00 000000
 D: 0:3 00 00 00 00 00 00 000000
 E: 1:0 00 00 00 00 00 00 000000
 F: 1:1 00 00 00 00 00 00 000000
 G: 1:2 00 00 00 00 00 00 000000
 H: 1:3 fd 99 00 60 00 00 000000
 I: 2:0 07 05 00 02 00 00 000000
 J: 2:1 00 00 00 00 00 00 000000
 K: 2:2 00 00 00 00 00 00 000000
 L: 2:3 00 00 00 00 00 00 000000
 M: 3:0 00 00 00 00 00 00 000000
 N: 3:1 00 00 00 00 00 00 000000
 O: 3:2 00 00 00 00 00 00 000000
 P: 3:3 00 00 00 00 00 00 000000
 Q: 4:0 00 00 00 00 00 00 000000
 R: 4:1 00 00 00 00 00 00 000000
 S: 4:2 80 80 00 00 00 00 000000
 T: 4:3 01 01 00 00 00 00 000000
 U: 5:0 00 00 00 00 00 00 000000
 V: 5:1 02 00 00 02 00 00 000000
 W: 5:2 00 00 00 00 00 00 000000
 X: 5:3 78 08 08 70 00 60 606000
 Y: 6:0 02 00 00 02 00 00 000000
 Z: 6:1 0e 08 08 04 00 06 020600
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 00 00 00 00 00 00 000000
CC: 7:0 12 00 00 10 00 12 121200
DD: 7:1 00 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000

We made a mistake that a byte is sent what we intent to in a while loop prior to catching it in logic analyzer. But actually the loop not work, so we can’t catch the CLK and MOSI wave which we thought to be. After we start the logic analyzer first, it’s Okay for Nano dev kit spi1.
External Media
Thanks

#8

There’s no problem for the GPIO setting. You can also read the pin mux REG 0x70003058 to confirm the pin setting if got problem for debug in future.

0x70003058: PINMUX_AUX_SPI1_SCK_0
E_PREEMP = 0x00000001 // [15:15] ENABLE [DISABLE=0,ENABLE=1]

      IO_RESET                                                = 0x00000001 // [15:15] IORESET [IORESET=1,NORMAL=0]

      DRV_TYPE                                                = 0x00000003 // [14:13] DRIVE_4X [DRIVE_1X=0,DRIVE_2X=1,DRIVE_3X=2,DRIVE_4X=3]

      E_SCHMT                                                 = 0x00000000 // [12:12] DISABLE [DISABLE=0,ENABLE=1]

      E_HSM                                                   = 0x00000000 // [09:09] DISABLE [DISABLE=0,ENABLE=1]

      LOCK                                                    = 0x00000000 // [07:07] DISABLE [DISABLE=0,ENABLE=1]

      E_INPUT                                                 = 0x00000001 // [06:06] ENABLE [DISABLE=0,ENABLE=1]

      PARK                                                    = 0x00000001 // [05:05] PARKED [NORMAL=0,PARKED=1]

      TRISTATE                                                = 0x00000001 // [04:04] TRISTATE [PASSTHROUGH=0,TRISTATE=1]

PUPD = 0x00000001 // [03:02] PULL_DOWN [NONE=0,PULL_DOWN=1,PULL_UP=2,RSVD=3]

      PM                                                      = 0x00000000 // [01:00] SPI1 [RSVD1=1,RSVD2=2,RSVD3=3,SPI1=0]
#9

Hi ShaneCCC,

Thanks

How to read “the pin mux REG”?

Thanks

#10

You can have use devmem2 to read it.

sudo apt-get install devmem2

#11

Thanks

#12