On a custom carrier board, RGMII Ethernet interface is directly connected to the SJA1105P switch. However, I’m unable to get the upstream (RGMII Orin<->SJA1105) link running from the Orin side:
Relevant device tree nodes (only changed lines are shown, the rest is the default configuration from tegra234-p3737-0000+p3701-0004-nv.dts file):
ethernet@2310000 {
status = "okay";
phy-mode = "rgmii-id";
nvidia,mac-addr-idx = <1>;
nvidia,pause-frames = <0>;
nvidia,max-platform-mtu = <1514>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
spi@3210000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&{/bus@0/pinmux@2430000/spi1_pins_config}>;
/delete-node/ spi@0;
spi@0 {
compatible = "nxp,sja1105p";
reg = <0>;
spi-max-frequency = <12000000>;
#address-cells = <0x01>;
#size-cells = <0x00>;
spi-cpha;
nvidia,cs-setup-clk-count = <1000>;
nvidia,cs-hold-clk-count = <1000>;
nvidia,cs-inactive-cycles = <1000>;
reset-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <16>;
nvidia,tx-clk-tap-delay = <0>;
nvidia,cs-setup-clk-count = <1000>;
nvidia,cs-hold-clk-count = <1000>;
nvidia,cs-inactive-cycles = <1000>;
};
ports {
/* other ports are skipped */
port@0 {
ethernet = <&{/bus@0/ethernet@2310000}>;
phy-mode = "rgmii-id";
reg = <0x00>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
Pinmux is configured as follows:
pinmux@2430000 {
pinctrl-names = "default";
pinctrl-0 = <
&{/bus@0/pinmux@2430000/eth_base_t1}
>;
eth_base_t1 {
phy_resets {
nvidia,pins =
"pex_l10_rst_n_pag7",
"pex_l7_rst_n_pag1",
"pex_l0_rst_n_pk1",
"pex_l8_rst_n_pag3";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
phy_irqs {
nvidia,pins =
"pex_l10_clkreq_n_pag6",
"pex_l7_clkreq_n_pag0",
"pex_l0_clkreq_n_pk0",
"pex_l8_clkreq_n_pag2";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
sja1105_reset {
nvidia,pins = "soc_gpio18_pg5";
nvidia,function = "rsvd0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
mdio {
nvidia,pins = "eqos_sma_mdio_pf4";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
mdc {
nvidia,pins = "eqos_sma_mdc_pf5";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
rgmii_tx {
nvidia,pins =
"eqos_txc_pe0",
"eqos_td0_pe1",
"eqos_td1_pe2",
"eqos_td2_pe3",
"eqos_td3_pe4",
"eqos_tx_ctl_pe5";
nvidia,function = "eqos";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
rgmii_rx {
nvidia,pins =
"eqos_rd0_pe6",
"eqos_rd1_pe7",
"eqos_rd2_pf0",
"eqos_rd3_pf1",
"eqos_rx_ctl_pf2",
"eqos_rxc_pf3";
nvidia,function = "eqos";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
spi1_pins_config {
spi1_sck_pz3 {
nvidia,pins = "spi1_sck_pz3";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi1_miso_pz4 {
nvidia,pins = "spi1_miso_pz4";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi1_mosi_pz5 {
nvidia,pins = "spi1_mosi_pz5";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi1_cs0_pz6 {
nvidia,pins = "spi1_cs0_pz6";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
};
};
SJA1105 is successfully probed and initialized, but initialization of the RGMII MAC fails with the following error messages:
[ 9.570004] sja1105 spi0.0: Probed switch chip: SJA1105P
[ 9.936679] nvethernet 2310000.ethernet: Adding to iommu group 54
[ 9.939927] nvethernet 2310000.ethernet: failed to read skip mac reset flag, default 0
[ 9.939933] nvethernet 2310000.ethernet: failed to read MDIO address
[ 9.939936] nvethernet 2310000.ethernet: Failed to read nvida,pause_frames, so setting to default support as disable
[ 9.939939] nvethernet 2310000.ethernet: setting to default DMA bit mask
[ 9.948648] nvethernet 2310000.ethernet: failed to get phy reset gpio error: -2
[ 9.953896] nvethernet 2310000.ethernet: Ethernet MAC address: 48:b0:2d:95:46:24
[ 9.957764] nvethernet 2310000.ethernet: macsec parameter is missing or disabled
[ 9.957768] nvethernet 2310000.ethernet: Macsec not supported/Not enabled
[ 9.958770] nvethernet 2310000.ethernet: eth1 (HW ver: 53) created with 8 DMA channels
[ 14.144223] sja1105 spi0.0: Probed switch chip: SJA1105P
[ 15.419434] nvethernet 2310000.ethernet: [poll_check][42][type:0x4][loga-0x0] poll_check: timeout
[ 15.419448] nvethernet 2310000.ethernet: ether_open: failed to initialize MAC HW core with reason -1
[ 15.465817] sja1105 spi0.0: configuring for fixed/rgmii-id link mode
[ 15.465947] nvethernet 2310000.ethernet eth1: Macsec not supported or not enabled in DT
[ 15.466976] sja1105 spi0.0: Link is Up - 1Gbps/Full - flow control off
What could be the general cause of the issue? In what direction to look? Issue occurs before any PHY initialization on downstream switch ports happens, therefore all PHY sections are omitted.