I want to process data from an FPGA and feed it to Tegra K1 jetson board. what’s the fasetst link available? is there a FMC equivalent connection or card that I can plug in TK1 with an FPGA? for now i have a FPGA dev board and want to stream the data to TegraK1 and use CUDA to do some DSP acceleration. but I must reduce the bottleneck between the two boards. any suggetions? thanks
A few questions here?
What is your bottleneck? Is it latency, memory or bandwidth?
What FPGA dev board you are using?
What interfaces does it have?
—Which FPGA interface you are most familiar with?
i’m interested in using xilinx zynq and its dev board. the bottle neck is the latency. need to transfer large amnt of data as fast as possible. i’m familiar with AXI interface. but now that i look at it i can perhaps take advantage of usb connections in zynq dev board and jetson board.
i need high bw and low latency… it’s for a real time dsp but fpga in zynq isn’t enough so i want to rely on tegra’s cpu and gpu for further dsp acceleration. zynq here is acting as a dumb device that samples and creates/stores data into a buffer and ship it out to tegra for the bulk of the processing. the brain is in tk1 not zynq fpga here.
A reminder that is the the Zynq onboard is USB 2.0.
Using the z706 or the z702?
I have both but primarily 702. TK1 needs something similar to FMC so that I can plug in RFIC or DACs directly to it.
do you do similar work?
I’ve considered similar questions, although not for a an FPGA. One route seems to go with just GPIO, and I’ve compiled a list of data for using some of the touchscreen/camera and other previously-designated GPIO so that I’d have more available (requires giving up some of the touchscreen/camera pins, but I’m not using this anyway). For that purpose, I’m building up a spreadsheet on what I might reassign from J3A1 or J3A2.
Here is what I found to be available as GPIO if you are willing to forgo the original use (excludes the 7 connector pins which are already just GPIO at J3A2…TEGRA_GPIO_PU0 through 6):
J3A1, pin 50, LCD_BL_PWM, TEGRA_GPIO_PH1
J3A1, pin 48, LCD_BL_EN, TEGRA_GPIO_PH2
J3A1, pin 11, TS_SHDN_L, TEGRA_GPIO_PK1
J3A1, pin 17, TS_IRQ_L, TEGRA_GPIO_PK2
J3A1, pin 13, TS_RESET_L, TEGRA_GPIO_PK4
J3A2, pin 4, CAM2_MCLK, TEGRA_GPIO_PBB0
J3A2, pin 5, CAM_RST_L, TEGRA_GPIO_PBB3
J3A2, pin 63, CAM_FLASH, TEGRA_GPIO_PBB4
J3A2, pin 66, CAM1_PWDN, TEGRA_GPIO_PBB5
J3A2, pin 2, CAM2_PWDN, TEGRA_GPIO_PBB6
J3A2, pin 60, CAM1_AF_DOWN, TEGRA_GPIO_PBB7
J3A2, pin 57, CAM1_GPIO, TEGRA_GPIO_PCC1
J3A2, pin 7, CAM2_GPIO, TEGRA_GPIO_PCC2
It looks like a bit of work, but giving up camera and touchscreen functions will yield an extra 13 GPIO which are capable of either data or interrupt use. Add in GPIO PU0 through PU6 and you have up to 20 GPIO.
The second option if you need bandwidth and low latency is the mPCIe x1 slot. I can’t personally use this option, I can’t afford a dev kit and I have no idea what chip would support simple PCIe use.
It might be of interest that the mPCIe slot has more than just the PCIe x1 data lane…it also has a USB lane (the DP/DM pair). As long as the PCIe slot were used though, I wouldn’t bother wiring it for USB.
Here’s my big question…can anyone recommend a single chip for PCIe single lane transceiver function? Something which handles the 10-bit encode/decode and TX/RX LVDS? I’d love to go with this option, but cannot afford the dev kit option. A single inexpensive chip on a 4-layer PCB might do the job.
TK1 itself and custom PCBs can support PCIe gen2 x4 (2000 MB/s). The Jetson’s mini-PCIe slot is limited to PCIe gen2 x1 (500 MB/s), although in practice people have trouble getting links with the Jetson @ gen2 (instead gen1 x1 250MB/s).
If you had an x1 FMC carrier card (for example [url]Sign in · Open Hardware Repository), one could connect it via PCIe/USB riser: [url]Amazon.com
Alternatively if the Zynq was available in mini-PCIe form factor, like this [url]http://www.geb-enterprise.com/PRODUCTS/PCIe_MINI.html[/url], you could mount it to the Jetson directly.