Tegra_vnet driver compatible with JetPack 5.1.2?

[smcentee]

Is there a more updated version of the tegra_vnet.c driver for the PCIe interface? We are this driver for PCIe communication and trying to upgrade to JetPack 5.1.2, but it gives us kernel panics and fails.

It works great with JetPack 4.6.3, but after we upgraded to 5.1.2, we experience kernel panics when the interface is up (no panics when the interface is not up, so that is how we think it is related to the PCIe interface). I have attached the kernel panic log, as well as a zip file with the tegra_vnet c, h, and makefile included for the tvnet driver we are using (previously provided to us my NVIDIA a while back).

Thank you for helping us out on this issue.
tvnet.zip (9.7 KB)

pcie_kernel_panic_log.txt (18.4 KB)

[WayneWWW]

Hi,

Please follow the document here to apply corresponding patch.

https://docs.nvidia.com/jetson/archives/r35.4.1/DeveloperGuide/text/SD/Communications/PcieEndpointMode.html?highlight=endpoint

[smcentee]

Thanks. I have applied the patches to the source file located at:

/kernel/kernel-5.10/drivers/pci/controller/dwc/pcie-tegra194.c

as zipped here (if you can confirm that is correct)
pcie-tegra194.zip (25.4 KB)

Then, do I need to recompile by running the Makefile in that folder? What is the next step after that (it doesn’t mention it in the documentation)?

Thanks!

[WayneWWW]

Rebuild the kernel image… put the new kernel image into /boot/Image on device or kernel/Image on your host PC Linux_for_Tegra directory and reflash the board…

[smcentee]

When I try to rebuild the kernel with the patched pcie-tegra194.c file, I receive this error:

Since the patch is commenting out that function:

#if 0
/* Reserve BAR0_BASE + BAR0_MSI_OFFSET of size SZ_64K as MSI page */
static int tegra_pcie_ep_set_bar(struct dw_pcie_ep *ep, u8 func_no,
struct pci_epf_bar *epf_bar)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
enum pci_barno bar = epf_bar->barno;
dma_addr_t msi_phy = epf_bar->phys_addr + BAR0_MSI_OFFSET;

if (pcie->gic_v2m && (bar == BAR_0)) {
appl_writel(pcie, lower_32_bits(msi_phy),
APPL_SEC_EXTERNAL_MSI_ADDR_L);
appl_writel(pcie, upper_32_bits(msi_phy),
APPL_SEC_EXTERNAL_MSI_ADDR_H);

  appl_writel(pcie, lower_32_bits(pcie->msi_base.start),
  	    APPL_SEC_INTERNAL_MSI_ADDR_L);
  appl_writel(pcie, upper_32_bits(pcie->msi_base.start),
  	    APPL_SEC_INTERNAL_MSI_ADDR_H);

}

return 0;
}
endif

Line 3969 calls that function:

static struct dw_pcie_ep_ops pcie_ep_ops = {

.raise_irq = tegra_pcie_ep_raise_irq,

.get_features = tegra_pcie_ep_get_features,

.set_bar = tegra_pcie_ep_set_bar,

};

which sets .set_bar = tegra_pcie_ep_set_bar,

Am I patching the file correctly? If not, can you provide me the patched file so I know it is correct and I can recompile my kernel for PCIe mode?

[WayneWWW]

please try to read the document carefully…

[smcentee]

Oh ok.

So I’m guessing the ‘-’ means remove that line…

static struct dw_pcie_ep_ops pcie_ep_ops = {
.raise_irq = tegra_pcie_ep_raise_irq,
.get_features = tegra_pcie_ep_get_features,
- .set_bar = tegra_pcie_ep_set_bar,
};

Missed that. I’ll remove and see if it compiles. Thanks.

[smcentee]

That compiled. Thanks.

Attached is the patched file (pcie-tegra194.c) for the AGX, if anyone else needs it.
pcie-tegra194.zip (25.4 KB)