hello XuanZZZ,
it’ll enable pixel parser when deskew calibration has done.
in other words, if you see below, it’s VI engine to start waiting for camera frames.
[ 146.899457] [RCE] nvcsi_stream_enable: enable pixel parser++ Line(3554)
[ 146.899458] [RCE] nvcsi_stream_enable: enable pixel parser-- Line(3591)
the clock has divide by 2 since data is sent on both rising/falling edges of clock.
for instance, you given pixel clock as 1.5Gbps, so, the RCE reported clock rate is.. 1.5 Gbps / 2 = 750 MHz
however,
there’re lots of PHY interrupts, [RCE] ISR PHY 0 CIL_A 0xe000000 has reported.
you may refer to Orin TRM for CILA_INTR_0_STATUS_CILA_0 register description. it’s reported by bit-25,26,27 which usually due to DPHY deskew calibration did not complete, it happened when the calibration sequence length is not long enough.
hence..
please try to configure cil_settletime, and, please also review the serdes_pix_clk_hz settings.