tx1 i2c write length limited in user zone.


I’m working on an encryption verification system now.I use a chip that call atsha204.We communicate via the I2C bus.But when the length of data that I write to i2c bus longer than 14.The i2c bus error occured.And the kernel dump this.

dmesg|tail -13
[ 1724.255774] Host read timeout at address 546c0d90
[ 1725.256140] tegra-vii2c 546c0000.i2c: --- register dump for debugging ----
[ 1725.766788] Host read timeout at address 546c0c00
[ 1725.768082] tegra-vii2c 546c0000.i2c: I2C_CNFG - 0xffffffff
[ 1726.274732] tegra-vii2c 546c0000.i2c: I2C_PACKET_TRANSFER_STATUS - 0xffffffff
[ 1726.781216] tegra-vii2c 546c0000.i2c: I2C_FIFO_CONTROL - 0xffffffff
[ 1727.287694] tegra-vii2c 546c0000.i2c: I2C_FIFO_STATUS - 0xffffffff
[ 1727.794174] tegra-vii2c 546c0000.i2c: I2C_INT_MASK - 0xffffffff
[ 1728.296714] tegra-vii2c 546c0000.i2c: I2C_INT_STATUS - 0xffffffff
[ 1728.296716] tegra-vii2c 546c0000.i2c: msg->len - 28
[ 1728.296718] tegra-vii2c 546c0000.i2c: is_msg_write - 1
[ 1728.296720] tegra-vii2c 546c0000.i2c: buf_remaining - 0
[ 1729.804329] tegra-vii2c 546c0000.i2c: i2c transfer timed out, addr 0x0064, data 0x03

The data I write is 28 bytes.The chip cannot allow me split the data to write,so I got a trouble.
Could anyone give me a hand?
Best Regards

We are investigating it. Means while could you try if the transfer size is not 4n+<0, 1,2,3> bytes for n=1,3,5,7,…, the size include the slave address.


I tried 32,33,34,35 bytes.It 's also not working

Best Regards

Can you please help get below detail informations to further check?

  1. I2C signal oscilloscope capture shots during the issue.
  2. Is the client driver user space or kernel space driver and what is API used for transfer.
  3. From the log, error is on I2C controller dedicated for camera and we have 2 different driver for generic i2c controller (i2c-tegra.c) and camera I2C driver (i2c-tegra-vi.c), If possible can this device be connected to Gen1 I2C and tested?

ANd do you use Jetpack 3.1?


I have tried i2c-0,it can send any bytes to client.

Could you give below information to help us figure out the root cause for the vii2c bus?

1.Could you please visit below two url for i2c-0 and i2c-6 capturers with logic analizer?
The two picturers capture by the same code in user space.I write 64 bytes to the client in this code.
Part of my code:

struct i2c_msg msg[2];
        u8 buf[4] = {0};
        int err;
        u8 buff[64];
        u16 crc;
        struct i2c_ioctl_rdwr_data msgst;




2.Whether in user space or kernel space,it’s the same situation.

3.I use Jetpack 3.1.And the kernel release is
Linux tegra-ubuntu 4.4.38+ #2 SMP PREEMPT Thu Sep 21 17:40:12 CST 2017 aarch64 aarch64 aarch64 GNU/Linux

I am currently looking into this issue.
I tried the same message pattern you mentioned on i2c-6 locally with HSEPROM (Part no: FM24V05) and do not see any issues.

Need few more details to check this further, could you please provide?

  • Complete UART log from the start of boot and test output?
  • Are there any other devices connected on i2c-6?
  • For write message, why ACK is ignored?

From kernel/kernel-4.4/drivers/media/platform/tegra/regmap_util.c:

/* bug 200048392 -
 * the vi i2c cannot take a FIFO buffer bigger than 16 bytes

Also my experience is that trying to write any more than 16 bytes to i2c-6 results in timeout.

Hi All
The issue is fixed by attached patch and should be have it in next release.
0001-i2c-tegra-vi-bypass-the-wait-for-pkt-transfer-done.patch.txt (2.32 KB)

Hi ShaneCCC
I use the BSP version is R24.2.1 the ‘tegra_i2c_reg_addr()’ function is undefined,could you give me a patch for R24.2.1? Thank you!

This patch is for r28.1, you have to back port it by youself.