TX2 header j21 pins mmap to memory address

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

Hello

I have a Jetson Development tx2 tegra board setup and running.

Using the Jetson Tx2 J21 header pinout document, I am using the pins:
gpio255 - GPIO_GEN3 pin 15,
gpio298 - GPI06 pin 31,
gpio388 - GPIO26 pin 37,

power and gnd
3.3 VDC - pin 1,
GND - pin 39.

I have got the pins functioning using the normal file descriptor approach:
echo 298 > export,
echo out > direction
echo 0 > value
echo 1 > value

The above approach works and it also is usable in c++ using open and write c functions.

Question.

I want to use the same pins but access them using memory map, mmap. Is it possible to lookup the memory addresses on the computer that has been allocated for the pin?

What is the sequance needed to:
a) get the moment address for the pin,
b) set the bit in order to make it GPIO rather than SFIO
c) Set the direction
d) set the pin high/low

Any extra helpful info for then using this in a c++ class?

also
Does it make any difference to the mmap function call if the file descriptors are exported or not?

Hope someone can help this is a brain twister… :)

Thanks
Regards
Mike

2

hello
For gpio389, its initialization value is 0. Do you know his initialization position? I want to change the initialization value to 1. Where should I go to make the operation?

3

Hi

goto “cd /sys/class/gpio/”

export the gpio pin you want

-echo 298 > export,

this will make a directory called gpio298, cd into the new directory.

then set the direction with this command
echo out > direction

then set the value:
echo 0 > value
echo 1 > value

The pin should go high then low.

any idea how to do the same thing with direct memory map mmap?

Thanks
regards
Mike

4

hi，
Those are the operations that are under the system, only if they are in the system.I want to set it directly in the kernel, to ensure that the power is in a high level state.
Thank you all the same

5

hello michael.short,

would like to have confirmation of your use-case.
are you going to use gpio pin to monitor specific memory address status?
for example,
you would like to use gpio298 to monitor tegra_register status, checking the register values and report high/low of the gpio pin?

6

Hello

Use-cases:-

aim is to get full access to the GPIO pins to control a stepper motor. I need to mmap the memory, setup the PAD_CTLs and setup the pin for output.

E.g.

If I export pin 388, echo 388 > export, then I can use the value pin and send the pin HIGH and LOW.
Pin 37, GPIO_PQ4 I.04 is one of the pins I want to use…
I have access to the pin 37 using base address of 0x02200000 with an offset of 0x10890

What I am having trouble with is setting up the making the pin usable but WITHOUT using the
command “echo 388 > export” ?

What is the correct pad control and offset and also the sequence to setup the output pin?

Thanks
regards
Mike

7

hello michael.short,

you could report the gpio definition in the device tree, and control it in the sensor driver.
please refer to below source files for reference. thanks

sources/hardware/nvidia/platform/t18x/quill/kernel-dts/quill-platforms/tegra186-quill-camera-imx274.dtsi
sources/kernel/kernel-4.4/drivers/media/i2c/imx274.c
8

Thanks

But, here are the steps I want to perform:-

1: I have mmap the memory.

2: Now I want to export the pin 388, not using the export function but rather the PAD_CTLs to assign the needed settings to make the export ready of the pin.

I need the base address for the correct PAD_CTL for that pin, and the offset that is needed also.
base address = ???
offset = ???

3: Once the pin has been setup on the correct PAD_CTL I can then send the pin HIGH and LOW as needed.

The information is in the Parker TRM, Please answer this question as requested with the information requested. I can not make a total out of the device tree information.

Thanks
regards
Mike

9

Within the kernel you should have access to physical address. The “system address map” of the relevant Technical Reference Manual, chapter two, table two, provides a base physical address of each controller within the TX2. All controllers are described in separate chapters based on offsets of the base physical address…offsets are the same for all controllers of that type, you’d just add that to the base address. GPIO controllers are included in this.

Go here (in some cases you may need to log in again if you don’t get to the downloads):
https://developer.nvidia.com/embedded/downloads

Put “technical reference manual” in the search box, look for:

Tegra X2 (Parker Series SoC) Technical Reference Manual

You will need your own kernel code to translate between user space and kernel space and to provide whatever interface is desired through that conversion (e.g., a device special file with ioctl control).