GPIO Base Address of Jetson TX2

Hello,

I have a simple question : what is the GPIO Base Address of the TX2 ? And which block size should I use ? I would like to use mmap to have a direct access to the GPIOs via /dev/mem.

Thanks :)

hello belosthomas,

you could found the tutorial in the Tegra Linux Driver Package TX2 Adaptation Guide from the GPIO changes chapter.
this documentation could be downloaded from Development Guide 28.1 Release–>PDF Documents–>Tegra Linux Driver Package TX2 Adaptation Guide.
thanks

Thank you. But I can not find the answer to my question in the document (or I do not understand). Here is some of my code :

#define GPIO_ADDR 0x???????? // I do not know what to put here
#define GPIO_BLOCK ??        // and here

...

this->fd = open("/dev/mem",O_RDWR);
if (this->fd < 0) {
	std::cerr << "Can't open /dev/mem" << std::endl;
	exit(EXIT_FAILURE);
}
	
gpioAddress = (unsigned long*)mmap(NULL, GPIO_BLOCK, PROT_READ | PROT_WRITE, MAP_SHARED, this->fd, GPIO_ADDR);
close(this->fd);

...

unsigned long aGpio = whatever you want
unsigned long value = *(gpioAddress + 1);
return (value & (1 < aGpio));

For exemple, on a RPi 3, i need to use GPIO_BASE= 0x20200000 ( BCM2708_PERI_BASE = 0x20000000 and GPIO is located at 0x00200000 ).

There is more than one GPIO controller in the Tegra chips. The Technical Reference Manual (TRM) lists which controller base address goes with which GPIO. This same controller address is used in the device tree during GPIO setup (the “gpio@c2f0000” and similar device tree entries refer to the particular controller being set up).

Thank you @Linuxdev. The controller I’m looking for is the one corresponding to the pin header attached to the jetson. I’ll search in the device tree entries.

Also i found this by typing gpio@c2f0000 on google :

https://www.kernel.org/doc/Documentation/devicetree/bindings/gpio/nvidia%2Ctegra186-gpio.txt

Have you checked the TRM? The software side has more than two controller base addresses…the controllers you are interested in share offsets within a single base address to deal with a bank of GPIO. The document you want is:

Parker_TRM_DP07821001p.pdf

https://developer.nvidia.com/embedded/downloads

In the document, chapter 2, table 2, “System Address Map”, you will find a series of “GPIO_CTL#_GPIO#” entries. This lists the base address of that group of GPIO. The chapter on GPIO talks about registers and offsets…these apply to any of those table 2 addresses.

The puzzle I think you are interested in solving is mapping a physical pin to a controller. Which pin of which header are you interested in? Here are threads regarding that topic:
https://devtalk.nvidia.com/default/topic/1003613/jetson-tx2/gpio-doesn-t-work-/post/5125910/#5125910
https://devtalk.nvidia.com/default/topic/1007639/jetson-tx2/how-do-i-map-signal-names-to-gpio-numbers-/post/5144174/#5144174

I’m actually trying to do the same thing as @belosthomas. At the moment, I’m not able to find a reasonable process to map a gpio pin number (for example, 398) to a physical machine address.

Did anyone find a way to solve this problem?

EDIT: Solved, after reading GPIO registers details from here http://developer2.download.nvidia.com/assets/embedded/secure/jetson/TX2/docs/Parker_TRM_DP07821001p.pdf?IgNqnEJcsdPQoY8HWnWh-6toG80N2J5DwKOUAEdicQW9vm3fq5IIQR_UJ9AuyKXdjKYokqo-bXdcWBXx0PmVw7FoJ1qaKHPwmcRwXpIzT0yPxwVGQddiju6xo8o6TrIS-1nhTbh3RfMSwxutlHjiRMSuAoX88weZ8U-jwfx4BQc.

Thanks anyway!