Use low_latency_mode=1 v4l2 is block

we use the TX2-NX board on Version 32.7.2
we use the camera ISX019,10fps, Due to hardware reasons, when we use the trigger signal, there will be a loss of 5 frames

while we use the normal v4l-ctl common like this

v4l2-ctl --set-ctrl --set-ctrl bypass_mode=0 --stream-mmap  -d /dev/video0

it can see like that

<<<<<<<<<< 10fps
<<<<<<<< 9fps
<<<<<<< 8fps
<<<<<<<<<< 9fps

This is reasonable and what we expected

while we use the low_latency_mode v4l-ctl common like this

v4l2-ctl --set-ctrl low_latency_mode=1 --set-ctrl bypass_mode=0 --stream-mmap  -d /dev/video0

it can see like that

<<<<<<<<<< 10fps
<<<<<

This will be blocked here

and dmesg show that always

tgra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
tgra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
tgra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
tgra-vi4 15700000.vi: ATMOP_FE syncpy timeout! err = -11
tgra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
......

But we can observe the mipi signal using an oscilloscope

Increase the timeout to try.

./vi/vi4_fops.c:        chan->timeout = msecs_to_jiffies(200);

1 Like

Thank you , the problem have be sloved

I would like to know if this modification will have any other negative effects

I don’t come out any negative effects, but we didn’t have complete test for the low latency mode.

By the way, is there no issue of two frames delay after version 35.0 on other platfrom like orin nx?

As my previous comment we don’t have a test case for the low latency mode for each release.

Thanks

Sorry, I may have misunderstood, only TEGRA_ 19x architecture does not require the use of low_latency_mode

Suppose yes, due to the VI5 driver implement is different with VI2/VI4.

thank you

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