VI/CSI bandwidth limitations with four 4-lane 24MP camera

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
1

Hello,

I am trying to connect four 4-lane CSI camera sensor (OV24A1B) transmitting 10-bit raw grayscale pixel. Each sensor is configured to 24 MegaPixel.

I would like to compute the maximal possible frame rate with the following characteristics:

  • 10-bit pixel
  • 24 MP per camera
  • 4 synchronous cameras
  • MIPI frequency at 1Gbps (up to 1.5 Gbps)

I am extracting the raw frames with the V4L2 API.

At the moment, I have broken frames at 7.5 FPS and a MIPI frequency at 1Gbps. Ideally, I would like to reach a frame rate of 15 FPS.

How can I compute my frame rate limitation based on the MIPI frequency and the internal limitations of the CSI and VI modules ?

Thanks in advance,

2

Could you try boost the clock by below command. Also run the jetson_clocks.sh

sudo su
echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate
cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate
cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate
echo {$max_rate} > /sys/kernel/debug/bpmp/debug/clk/vi/rate
echo {$max_rate} > /sys/kernel/debug/bpmp/debug/clk/isp/rate
echo {$max_rate} > /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate
3

Hello,

My clocks for the following devices:

-VI
-ISP
-NVCSI

were already at their maximal range.

I would like to know if there is a way to modify the NVCSI/VI pipeline to better fit my usecase and therefore increase the maximal frame rate.

How can I compute the theoretical maximal bandwidth of the video pipeline (from CSI capture to the memory copy) ?

Thanks in advance,

4

Hello,

Is it possible to hold a telco with you during European time zone working hours ?

Thanks in advance,

5

@Mobilaz
Does single sensor can reach 15fps?
Could you also boost the memory clock to check if help. “/sys/kernel/debug/bpmp/debug/clk/emc”

6

@Mobilaz
Theoretically single 24M@15fps should be ok.
If you boost all clocks still can’t get 25fps on single sensors that could be the sensor output not at 15fps.

7

Hello,

Indeed, a single sensor at 15fps works fine.

Modifying the emc’s clock did not change the result.

Whenever, I tried to use 4 sensor at 15fps, I have these messages in the kernel logs:

tegra194-vi5 15c10000.vi: vi_capture_status : no reply from camera processor
tegra194-vi5 15c10000.vi: vi_capture_status : no reply from camera processor
tegra194-vi5 15c10000.vi: vi capture dequeue status failed
tegra194-vi5 15c10000.vi: vi capture dequeue status failed
tegra194-vi5 15c10000.vi: vi_capture_status : no reply from camera processor
tegra194-vi5 15c10000.vi: vi capture dequeue status failed

Do you know how I could patch the CSI/VI pipepline to alleviate the video storing process ?

Thanks in advance,

8

Looks like got bandwidth problem to 424M15fps, what’s your use case need 424M?

9

Has this issue been resolved? Is it now possible to process 4, 24MP camera streams @ 15 fps in real time? Or is there an aggregate stream limit to the software which is lower than the supported hardware limit?

We have a similar high-BW application we’d like to address:
2, 48MP cameras, 10-bits per pixel
4 lanes CSI-2 @ 2.5Gb/s per lane => 10Gb/s per camera

Theoretical max. frame rate = 21 frames/s (no overhead)

We’d like to run 2 cameras @ 19 fps. Is this possible with AGX or would we hit BW limitations in the software before reaching 19fps? If so, at what point?