way to control Fermi's caches?

Is there any way to control Fermi’s L1 cache using OpenCL as CUDA ? Perhaps an extension or it is automatically setup based on the amount of shared memory requested by the kernel?

I am curious about this too…
Seems by default you might get 48k share mem? (as that is what oclDeviceQuery returns…)
This would be ideal for an NV_ extension.

I’ve been searching the solution for a while but haven’t found idea. I guess Nvidia hasn’t provided any API to control L1 for OpenCL yet. If you have any ideas please post here.