What's difference of tegra camera platform from AGX Xavier to AGX Orin?

[SammyChenTw]

I had use FPGA for HDMI video to MIPI CSI on Xavier, and it could play video by /dev/video0 on AGX Xavier.

How to disable CSI mipi CRC check on Xavier?

Hi, @ShaneCCC : We use the FPGA for HDMI video to MIPI CSI, video format YUV422, resolution 1920x1080xP60. HDMI video 1920x1080xP60 → FPGA → MIPI CSI 4 Lanes / YUV422 The FPGA convert the HDMI video into MIPI CSI format and is connected to MIPI CSI interface 4 Lanes(CSI A, CSI B) of Xavier As below block diagram: [Xavier_FPGA_MIPI_CSI] . Our CRC of FPGA mipi output doesn’t match Nvidia CSI CRC algorithm, but it is working after disable CRC patch on TX2. See post: HDMI FPGA to TX2 MIPI C…

I move this deivce tree from AGX Xavier to AGX Orin L4T R34.1.1, and driver can probe and pass the v4l2_async_register_subdev(), but it can’t see /dev/video0.
May I to know what’s difference of tegra camera platform from AGX Xavier to AGX Orin?
or any suggetion for debugging root cuase?

[ShaneCCC]

The vi@ scope change to tegra-capture-vi {} have reference to tegra234-camera-e3333-a00.dtsi to know the detail.

[SammyChenTw]

I change vi to tegra-capture-vi in device tree, but result are same, and can’t see /dev/video0.

I check the media0 topology, and it are empty:

# media-ctl --device /dev/media0 --print-topology
Media controller API version 5.10.65

Media device information
------------------------
driver          tegra-camrtc-ca
model           NVIDIA Tegra Video Input Device
serial          
bus info        
hw revision     0x3
driver version  5.10.65

Device topology

[ShaneCCC]

Review the device tree depend on reference sensor board.
Also check the driver probe() message.

[SammyChenTw]

I review the device tree and probe, and it could create /dev/video0 now.
But I can’t see video after vlc play /dev/video0, and see some tegra-capture-vi errors in dmsg log.

[  235.744440] tegra-camrtc-capture-vi tegra-capture-vi: uncorr_err: request timed out after 2500 ms
[  235.744714] tegra-camrtc-capture-vi tegra-capture-vi: err_rec: attempting to reset the capture channel

dmesg_log_vlc_play_20220817.txt (134.0 KB)

[ShaneCCC]

Review the pix_clk_hz/serdes_pix_clk_hz for the output data rate.

Skew calibration is required if sensor or deserializer is using DPHY, and the output data rate is > 1.5Gbps.
An initiation deskew signal should be sent by sensor or deserializer to perform the skew calibration. If the deskew signals is not sent, the receiver will stall, and the capture will time out.
You can calculate the output data rate with the following equation:

Output data rate = (sensor or deserializer pixel clock in hertz) * (bits per pixel) / (number of CSI lanes)

[SammyChenTw]

@ShaneCCC

An initiation deskew signal should be sent by sensor or deserializer to perform the skew calibration

May I to know what’s initiation deskew signal should be sent by FPGA to perform the skew calibration?
Could you proive a sample signal format?

[ShaneCCC]

Please check the DPHY datasheet.

Thanks

[SammyChenTw]

1. My FPGA resolution are 1920x1080x60P(YUV422), and output data rate is below 1.5Gbps.
   It could get video some time, and the rate of video success/NO video are 20%/80%.

2.I check the sensor DPHY datasheet, and which deskew mode need to set? Auto initial deskew on?

[ShaneCCC]

If the output data rate < 1.5Gbps you can ignore the deskew cal.
Your case could be the settle time cause the issue.
Please make sure the timing as below.