Customized HDMI2CSI 2 channels adapter on Orin

1.We are developing CRC enabled feature for our customized HDMI2CSI 2 channel adapter.
2.It can display 2 channel video streams on Xavier R35.1 correctly, but only first channel is correct on Orin, the 2nd channel can’t display video correctly.
3.The input video source is 1080p60, and format is YUV422/UYVY.
4.Test result
patch camera image is from How to disable CSI mipi CRC check on Orin? - #4 by jb035.cheng
5.Device tree configuration and Log files (2.5 MB)

hello jb035.cheng,

there shows PHY interrupts.
according to error code, it indicate there’re more than one bit error detected on the data lane [A/B] sync word.
for example,

     kworker/4:3-415     [004] ....   305.612584: rtcpu_nvcsi_intr: tstamp:10731081823 class:GLOBAL type:PHY_INTR0 phy:1 cil:0 st:0 vc:0 status:0x00000044
     kworker/4:3-415     [004] ....   305.612585: rtcpu_nvcsi_intr: tstamp:10731081823 class:GLOBAL type:PHY_INTR0 phy:1 cil:1 st:0 vc:0 status:0x00000044

could you please try using GPIO numbers instead of marco for controlling the pin,
for example, reset-gpio = <&tegra_main_gpio TEGRA234_MAIN_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
you may check # cat /sys/kernel/debug/gpio | grep PH.03 and assign the pin number directly for testing.

Currently, our adapter does not handle the reset pin.
I use two ways to reset, the first one is reset by GPIO script, and the other is by repluging the power of our adapter. Here are the log files. (2.1 MB)

hello jb035.cheng,

am still seeing PHY interrupts present on VI tracing logs.
could you please try apply this rce firmware Topic239397_Jan18.7z (201.3 KB) to test again?

you should update binary file, i.e. $OUT/Linux_for_Tegra/bootloader/camera-rtcpu-t234-rce.img
and perform partition flash to update camera firmware, i.e. $ sudo ./ -r -k A_rce-fw jetson-agx-orin-devkit mmcblk0p1

I use qv4l2 to open video0 and video1 one by one, the video0 is fine, but video1 will get lots of messages. (2.6 MB)

hello jb035.cheng,

it looks like timing issue, and mp740n1 debug prints also looks strange.
as you can see in 3_onebyone.txt.
for example,
when you open video0, it takes around 5-sec to enable camera stream, and your mp740n1 debug prints shows reasonable data.

[  779.795773] video0 by q4l2
[  800.495869] video0 by qv4l2-1080p60-UYVY
[  800.495921] =============================================================
[  805.299698] mp740n1 2-0032: get_chipid=0x0405 
[  805.300306] mp740n1 2-0032: Vactive=1080
[  805.300898] mp740n1 2-0032: Hactive=1920
[  805.301466] mp740n1 2-0032: no_signal=0
[  805.351547] [RCE] tegra_nvcsi_stream_set_config(vm0, stream=0, csi=0)
[  805.351569] [RCE] nvcsi_stream_enable: enable_pixel_parser Line(3437)

this is what you did for video1.
what happened between your step-3 and step-4?
besides, it’s taking around 11-sec from you issue qv4l2-1080p60-UYVY till mp740n1 debug logs prints.
those Vactive and Hactive=0 looks invalid, and what’s the circumstances to show this no_signal=1 message?

[  867.008700] video1 by q4l2
[  907.821939] video1 by qv4l2-1080p60-UYVY
[  907.821988] =============================================================
[  918.697701] mp740n1 2-0033: get_chipid=0x0000 
[  918.698235] mp740n1 2-0033: Vactive=0
[  918.698763] mp740n1 2-0033: Hactive=0
[  918.699828] mp740n1 2-0033: no_signal=1

since this is already no frames…
it’s error reported by VI side, and also the same PHY interrupts as present on VI tracing logs.

[  918.788455] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, status: 14, flags: 0 err_data 131072
[  918.799680] tegra-camrtc-capture-vi tegra-capture-vi: capture_status 14,CAPTURE_STATUS_FALCON_ERROR
[  918.850119] [RCE] ISR PHY 1 CIL_A 0x44
[  918.850120] [RCE] ISR PHY 1 CIL_A 0x44

We will fix the incorrect values by getting the correct value from I2C for channel2.
Since the driver is same for Orin and Xavier, are the handling different in Orin and Xaiver ?

hello jb035.cheng,

that should be the same, since Orin and Xavier series were sharing the same driver.

I fixed the incrooret values.
I can not get video1 correctly on Orin, but Xavier is correct.
Attached is the log and script files.

Below are my procedures
1.Start to record dmesg by dmesg -w |& tee -a 0_dmesg.txt
2.Execute to record trace log
3.Open video0 by qv4l2 to make sure the video0 stream is alive
4.Execute to open video0 and video1 one by one.
5.ctrl+c to stop procedure 1 and 2. (13.1 MB)

hello jb035.cheng,

let’s narrow down the issue, could you enable these two streams individually?
please enable gst pipeline with v4l2src plugin directly for checking the basic stream functionality.

or, you may check with v4l standard IOCTL…
for example, $ v4l2-ctl -d /dev/videoX --set-fmt-video=width=1920,height=1080,pixelformat=UYVY --set-ctrl bypass_mode=0 --stream-mmap --stream-count=100

I write the test procedures in readme.txt, zip file includes the test scripts and log files. (10.0 MB)

Is there any update for this ?

Do I need to do more tests, and get more logs to progress the debug ?
Please let me know how to imporve the debug, thanks.

Is there any update for this ?

Is there any update for this ?

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