Hello,
I wanted to know SPI1_MOSI , D55 pin of CVM connector connected to which pin of Tegra
GPIO?
I found that Table 3-4. 40-Pin Expansion Header Pin Description in the document "NVIDIA Jetson AGX Xavier Developer Kit Carrier Board Specification "SP-09778-001_v2.1 has wrong or not mentioned.
AND
I would like to know why the J503 is not explained in the same document?