jetson@tegra-ubuntu:~$ sudo devmem2 0X3D710
/dev/mem opened.
Memory mapped at address 0xffffba62e000.
Value at address 0x3D710 (0xffffba62e710): 0xFFFFFFFF
jetson@tegra-ubuntu:~$ sudo devmem2 0X3D710 w 0x101
/dev/mem opened.
Memory mapped at address 0xffff98af8000.
Value at address 0x3D710 (0xffff98af8710): 0xFFFFFFFF
Written 0x101; readback 0xFFFFFFFF
Please let us know the if any correction in accessing the address and point the correct address if any thing wrong .
please help to get the base address of below register NVCSI_PHY_2_NVCSI_CIL_CPHY_BIST_CONFIG_0_0
After referring the TRM(Orin-TRM_DP10508002_v1.2p) manual
we got few address related to PHY_2 as shown below and tried to access them, but its not working.
We have tried with 0x15a00000. When we read it is always 0xFFFFFFFF and after writing different values also it is showing 0xFFFFFFFF
nvidia@tegra-ubuntu:~$ sudo devmem2 0x15A0C710
/dev/mem opened.
Memory mapped at address 0xffffb2897000.
Value at address 0x15A0C710 (0xffffb2897710): 0xFFFFFFFF
jetson@tegra-ubuntu:~$ sudo devmem2 0x15A0C710 w 0x00000009
/dev/mem opened.
Memory mapped at address 0xffff996af000.
Value at address 0x15A0C710 (0xffff996af710): 0xFFFFFFFF
Written 0x9; readback 0xFFFFFFFF
As per the adaptation guide, only UPHY0 can be configured as USB. So our understanding is that the address what you are saying is related to UPHY0. Is it correct?
We are using UPHY2 lane4 for MGBE, so we need to configure the UPHY2 lane4 registers of Tx and Rx lines for PRBS. Can you help on this.