Hi Jerry.
On Sensor Software Driver Programming Guide, we have two options to build the driver, V4L2 Kernel Driver (Version 1.0) and V4L2 Kernel Driver (Version 2.0).
I’m building my driver on version 1.0, and I can see the /dev/video0 on system. But if I try to use nvarguscamerasrc on gstreamen it says that there’s no camera on system. So my question is: To work with libArgus, can I build driver on any version?
Thanks!
hello alfredosalvarani,
it use different camera frameworks for these two version of the V4L2 kernel drivers.
you may check reference drivers for the details of implementation.
for example,
version-1.0, $l4t-r32.2/public_sources/kernel_src/kernel/nvidia/drivers/media/i2c/imx185_1.c
version-2.0, $l4t-r32.2/public_sources/kernel_src/kernel/nvidia/drivers/media/i2c/imx185.c
nvarguscamerasrc adapt with these two different driver versions,
according to Camera Architecture Stack, there’re several approaches to work with camera drivers,
you may also check Approaches for Validating and Testing the V4L2 Driver, for accessing with V4L2 standard controls directly.
such a failure should usually a device tree issue, or driver implementation defects.
suggest you may refer to Debugging Tips to review your drivers.
thanks
Hello Jerry,
Follow you message on this: https://devtalk.nvidia.com/default/topic/1042759/jetson-tx2/nvcsi-on-the-jetsontx2-for-custom-driver/post/5289826/#5289826, I started to build my driver again using the tc358840.c as a reference, and it’s is better now. The driver don’t crash anymore.
But, when I try to capture video whith gstreamer nothing is showing in the screen and this error is reported on terminal:
[ 482.083963] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 482.090485] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 482.301537] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 482.308027] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
I’m sending my driver code and my DT attached.
Can you help-me on this? Can you check my driver/DT and tell me what is wrong?
Thanks.
adv7280.c (42.6 KB)
tegra186-quill-p3310-1000-c03-00-base.dts.txt (9.96 KB)
hello alfredosalvarani,
Thanks for you reply:
gst-launch-1.0 -v v4l2src ! 'video/x-raw, framerate=(fraction)30/1' ! nvoverlaysink
gst-launch-1.0 -v v4l2src ! 'video/x-raw, framerate=(fraction)30/1' ! autovideosink
gst-launch-1.0 -v v4l2src ! autovideosink
And also I tried v4l-ctl:
v4l2-ctl -d /dev/video0 --set-fmt-video width=720,height=576 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=10 --stream-to=f.raw
nvidia@nvidia-desktop:~$ v4l2-compliance -d /dev/video0
v4l2-compliance SHA : not available
Driver Info:
Driver name : tegra-video
Card type : vi-output, adv7280 6-0021
Bus info : platform:15700000.vi:0
Driver version: 4.9.140
Capabilities : 0x84200001
Video Capture
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04200001
Video Capture
Streaming
Extended Pix Format
Compliance test for device /dev/video0 (not using libv4l2):
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second video open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 1 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
fail: v4l2-test-io-config.cpp(174): TIMINGS cap not set, but could still get timings
fail: v4l2-test-io-config.cpp(253): Timings check failed for input 0.
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: FAIL
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Test input 0:
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
fail: v4l2-test-controls.cpp(633): did not check against size
test VIDIOC_G/S/TRY_EXT_CTRLS: FAIL
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 6 Private Controls: 12
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK (Not Supported)
test Scaling: OK
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
Test input 0:
Total: 43, Succeeded: 41, Failed: 2, Warnings: 0
I think it’s because of function adv7180_g_dv_timings, I’ve added it to my driver, because of this tegra code:
static void tegra_channel_populate_dev_info(struct tegra_camera_dev_info *cdev,
struct tegra_channel *chan)
{
u64 pixelclock = 0;
if (chan->pg_mode)
cdev->sensor_type = SENSORTYPE_VIRTUAL;
else if (v4l2_subdev_has_op(chan->subdev_on_csi,
video, g_dv_timings)) {
cdev->sensor_type = SENSORTYPE_OTHER;
pixelclock = tegra_channel_get_max_source_rate();
} else {
cdev->sensor_type = tegra_channel_get_sensor_type(chan);
pixelclock = tegra_channel_get_max_pixelclock(chan);
/* Multiply by CPHY symbols to pixels factor. */
if (cdev->sensor_type == SENSORTYPE_CPHY)
pixelclock *= 16/7;
cdev->lane_num = tegra_channel_get_num_lanes(chan);
}
cdev->pixel_rate = pixelclock;
cdev->pixel_bit_depth = chan->fmtinfo->width;
cdev->bpp = chan->fmtinfo->bpp.numerator;
/* BW in kBps */
cdev->bw = cdev->pixel_rate * cdev->bpp / 1024;
}
The if on line 8 is true because of my driver function “adv7180_g_dv_timings” and the else part (line 12) doesn’t run (my previous driver crash there)
But adv7180_g_dv_timings is a kind of dummy, and I need to take a look and develop it correctly. I don’t know if it will solve my problem, do you have any documentation to help me in this?
Thanks
Jerry, I’m looking on Property-Value Pairs, can you help on this?
compatible OK
reg OK
mclk I’m using extperiph1 by now, but my chip has a XTAL and don’t a clock supply from Jetson.
-gpio We don’t use GPIO, the pwrdwn amd reset pins of the chip, are connected on a “GPIO expander” controlled by I2C and I’ll change the driver to control these pins (by I2C) soon, by now these pins is always on.
-supply There’s no specific power supply to this chip, it’s always supplied by the main power supplier.
-reg Also there’s not regulator connected to chip.
physical_w
physical_h The chip is not a CCD sensor, it’s a bridge, where can I find these values?
sensor_model* OK
set_mode_delay_ms* Don’t know
post_crop_frame_drop* Don’t know
use_decibel_gain* Don’t know
delayed_gain* Don’t know
hello alfredosalvarani,
tc358840@1f {
compatible = "toshiba,tc358840";
reg = <0x1f>;
/* Physical dimensions of sensor */
physical_w = "4.713";
physical_h = "3.494";
Hi Jerry,
I enabled the VI tracer, and there is the log:
# tracer: nop
#
# entries-in-buffer/entries-written: 873/873 #P:4
#
# _-----=> irqs-off
# / _----=> need-resched
# | / _---=> hardirq/softirq
# || / _--=> preempt-depth
# ||| / delay
# TASK-PID CPU# |||| TIMESTAMP FUNCTION
# | | | |||| | |
kworker/5:1-8029 [005] .... 2512.789173: rtos_queue_peek_from_isr_failed: tstamp:78890942488 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2512.957155: rtos_queue_peek_from_isr_failed: tstamp:78895942492 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2513.125139: rtos_queue_peek_from_isr_failed: tstamp:78900942540 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2513.293122: rtos_queue_peek_from_isr_failed: tstamp:78905942507 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2513.461139: rtos_queue_peek_from_isr_failed: tstamp:78910942514 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2513.573115: rtos_queue_peek_from_isr_failed: tstamp:78915942560 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2513.741139: rtos_queue_peek_from_isr_failed: tstamp:78920942526 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2513.909159: rtos_queue_peek_from_isr_failed: tstamp:78925942532 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2514.077141: rtos_queue_peek_from_isr_failed: tstamp:78930942541 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2514.245139: rtos_queue_peek_from_isr_failed: tstamp:78935942549 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2514.413166: rtos_queue_peek_from_isr_failed: tstamp:78940942596 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2514.581152: rtos_queue_peek_from_isr_failed: tstamp:78945942561 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2514.693188: rtos_queue_peek_from_isr_failed: tstamp:78950942606 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2514.861180: rtos_queue_peek_from_isr_failed: tstamp:78955942573 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2515.029161: rtos_queue_peek_from_isr_failed: tstamp:78960942582 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2515.197156: rtos_queue_peek_from_isr_failed: tstamp:78965942589 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2515.365187: rtos_queue_peek_from_isr_failed: tstamp:78970942595 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2515.533195: rtos_queue_peek_from_isr_failed: tstamp:78975942643 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2515.701171: rtos_queue_peek_from_isr_failed: tstamp:78980942615 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2515.813151: rtos_queue_peek_from_isr_failed: tstamp:78985942617 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2515.981201: rtos_queue_peek_from_isr_failed: tstamp:78990942667 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2516.149176: rtos_queue_peek_from_isr_failed: tstamp:78995942630 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2516.317172: rtos_queue_peek_from_isr_failed: tstamp:79000942636 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2516.485207: rtos_queue_peek_from_isr_failed: tstamp:79005942642 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2516.653196: rtos_queue_peek_from_isr_failed: tstamp:79010942651 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2516.821184: rtos_queue_peek_from_isr_failed: tstamp:79015942701 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2516.933247: rtos_queue_peek_from_isr_failed: tstamp:79020942664 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2517.101239: rtos_queue_peek_from_isr_failed: tstamp:79025942717 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2517.269197: rtos_queue_peek_from_isr_failed: tstamp:79030942677 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2517.437195: rtos_queue_peek_from_isr_failed: tstamp:79035942683 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2517.605192: rtos_queue_peek_from_isr_failed: tstamp:79040942689 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2517.773183: rtos_queue_peek_from_isr_failed: tstamp:79045942698 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2517.941230: rtos_queue_peek_from_isr_failed: tstamp:79050942726 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2518.053189: rtos_queue_peek_from_isr_failed: tstamp:79055942712 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2518.165206: rtos_queue_peek_from_isr_failed: tstamp:79058077127 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2665.566862: rtos_queue_peek_from_isr_failed: tstamp:83664618629 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2665.566875: rtcpu_start: tstamp:83664620258
kworker/5:1-8029 [005] .... 2665.566881: rtos_queue_send_from_isr_failed: tstamp:83664629498 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2665.566885: rtos_queue_send_from_isr_failed: tstamp:83664629605 queue:0x0b4aad68
kworker/5:1-8029 [005] .... 2665.566888: rtos_queue_send_from_isr_failed: tstamp:83664629713 queue:0x0b4ac998
kworker/5:1-8029 [005] .... 2665.566890: rtos_queue_send_from_isr_failed: tstamp:83664629821 queue:0x0b4ae518
kworker/5:1-8029 [005] .... 2665.566893: rtos_queue_send_from_isr_failed: tstamp:83664629924 queue:0x0b4af2d8
kworker/5:1-8029 [005] .... 2665.566895: rtos_queue_send_from_isr_failed: tstamp:83664630029 queue:0x0b4b0098
kworker/5:1-8029 [005] .... 2665.566898: rtos_queue_send_from_isr_failed: tstamp:83664630134 queue:0x0b4b0e58
kworker/5:1-8029 [005] .... 2665.566900: rtos_queue_send_from_isr_failed: tstamp:83664630239 queue:0x0b4b1c18
kworker/5:1-8029 [005] .... 2665.566904: rtos_queue_send_failed: tstamp:83664630750 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2665.566907: rtos_queue_send_from_isr_failed: tstamp:83664633192 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2665.566909: rtos_queue_send_from_isr_failed: tstamp:83664633306 queue:0x0b4aad68
kworker/5:1-8029 [005] .... 2665.566912: rtos_queue_send_from_isr_failed: tstamp:83664633412 queue:0x0b4ac998
kworker/5:1-8029 [005] .... 2665.566914: rtos_queue_send_from_isr_failed: tstamp:83664633519 queue:0x0b4ae518
kworker/5:1-8029 [005] .... 2665.566917: rtos_queue_send_from_isr_failed: tstamp:83664633626 queue:0x0b4af2d8
kworker/5:1-8029 [005] .... 2665.566919: rtos_queue_send_from_isr_failed: tstamp:83664633736 queue:0x0b4b0098
kworker/5:1-8029 [005] .... 2665.566921: rtos_queue_send_from_isr_failed: tstamp:83664633840 queue:0x0b4b0e58
kworker/5:1-8029 [005] .... 2665.566924: rtos_queue_send_from_isr_failed: tstamp:83664633945 queue:0x0b4b1c18
kworker/5:1-8029 [005] .... 2665.566926: rtos_queue_send_failed: tstamp:83664634907 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2665.734876: rtos_queue_peek_from_isr_failed: tstamp:83669619015 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2665.790899: rtos_queue_send_from_isr_failed: tstamp:83671631649 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2665.790907: rtos_queue_send_from_isr_failed: tstamp:83671631792 queue:0x0b4aad68
kworker/5:1-8029 [005] .... 2665.790909: rtos_queue_send_from_isr_failed: tstamp:83671631932 queue:0x0b4ac998
kworker/5:1-8029 [005] .... 2665.790912: rtos_queue_send_from_isr_failed: tstamp:83671632072 queue:0x0b4ae518
kworker/5:1-8029 [005] .... 2665.790914: rtos_queue_send_from_isr_failed: tstamp:83671632209 queue:0x0b4af2d8
kworker/5:1-8029 [005] .... 2665.790916: rtos_queue_send_from_isr_failed: tstamp:83671632347 queue:0x0b4b0098
kworker/5:1-8029 [005] .... 2665.790919: rtos_queue_send_from_isr_failed: tstamp:83671632484 queue:0x0b4b0e58
kworker/5:1-8029 [005] .... 2665.790921: rtos_queue_send_from_isr_failed: tstamp:83671632623 queue:0x0b4b1c18
kworker/5:1-8029 [005] .... 2665.790925: rtos_queue_send_failed: tstamp:83671633366 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2665.790928: rtos_queue_send_from_isr_failed: tstamp:83671696901 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2665.790930: rtos_queue_send_from_isr_failed: tstamp:83671697046 queue:0x0b4aad68
kworker/5:1-8029 [005] .... 2665.790933: rtos_queue_send_from_isr_failed: tstamp:83671697186 queue:0x0b4ac998
kworker/5:1-8029 [005] .... 2665.790935: rtos_queue_send_from_isr_failed: tstamp:83671697326 queue:0x0b4ae518
kworker/5:1-8029 [005] .... 2665.790937: rtos_queue_send_from_isr_failed: tstamp:83671697463 queue:0x0b4af2d8
kworker/5:1-8029 [005] .... 2665.790940: rtos_queue_send_from_isr_failed: tstamp:83671697602 queue:0x0b4b0098
kworker/5:1-8029 [005] .... 2665.790942: rtos_queue_send_from_isr_failed: tstamp:83671697738 queue:0x0b4b0e58
kworker/5:1-8029 [005] .... 2665.790945: rtos_queue_send_from_isr_failed: tstamp:83671697880 queue:0x0b4b1c18
kworker/5:1-8029 [005] .... 2665.790948: rtos_queue_send_failed: tstamp:83671698444 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2665.790950: rtos_queue_send_from_isr_failed: tstamp:83671705351 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2665.790952: rtos_queue_send_from_isr_failed: tstamp:83671705490 queue:0x0b4aad68
kworker/5:1-8029 [005] .... 2665.790955: rtos_queue_send_from_isr_failed: tstamp:83671705629 queue:0x0b4ac998
kworker/5:1-8029 [005] .... 2665.790957: rtos_queue_send_from_isr_failed: tstamp:83671705767 queue:0x0b4ae518
kworker/5:1-8029 [005] .... 2665.790959: rtos_queue_send_from_isr_failed: tstamp:83671705905 queue:0x0b4af2d8
kworker/5:1-8029 [005] .... 2665.790962: rtos_queue_send_from_isr_failed: tstamp:83671706041 queue:0x0b4b0098
kworker/5:1-8029 [005] .... 2665.790964: rtos_queue_send_from_isr_failed: tstamp:83671706198 queue:0x0b4b0e58
kworker/5:1-8029 [005] .... 2665.790966: rtos_queue_send_from_isr_failed: tstamp:83671706334 queue:0x0b4b1c18
kworker/5:1-8029 [005] .... 2665.790969: rtos_queue_send_failed: tstamp:83671706908 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2665.790971: rtos_queue_send_from_isr_failed: tstamp:83671710470 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2665.790974: rtos_queue_send_from_isr_failed: tstamp:83671710610 queue:0x0b4aad68
kworker/5:1-8029 [005] .... 2665.790976: rtos_queue_send_from_isr_failed: tstamp:83671710750 queue:0x0b4ac998
kworker/5:1-8029 [005] .... 2665.790979: rtos_queue_send_from_isr_failed: tstamp:83671710889 queue:0x0b4ae518
kworker/5:1-8029 [005] .... 2665.790981: rtos_queue_send_from_isr_failed: tstamp:83671711045 queue:0x0b4af2d8
kworker/5:1-8029 [005] .... 2665.790984: rtos_queue_send_from_isr_failed: tstamp:83671711182 queue:0x0b4b0098
kworker/5:1-8029 [005] .... 2665.790986: rtos_queue_send_from_isr_failed: tstamp:83671711320 queue:0x0b4b0e58
kworker/5:1-8029 [005] .... 2665.790989: rtos_queue_send_from_isr_failed: tstamp:83671711459 queue:0x0b4b1c18
kworker/5:1-8029 [005] .... 2665.790991: rtos_queue_send_failed: tstamp:83671712913 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2665.846912: rtos_queue_peek_from_isr_failed: tstamp:83674619007 queue:0x0b4b4500
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kworker/5:1-8029 [005] .... 2667.146941: rtos_queue_peek_from_isr_failed: tstamp:83714619050 queue:0x0b4b4500
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kworker/5:1-8029 [005] .... 2667.315040: rtos_queue_send_failed: tstamp:83719780611 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2667.482976: rtos_queue_peek_from_isr_failed: tstamp:83724619094 queue:0x0b4b4500
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kworker/5:1-8029 [005] .... 2668.098924: rtos_queue_peek_from_isr_failed: tstamp:83744619093 queue:0x0b4b4500
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kworker/5:1-8029 [005] .... 2668.266906: rtos_queue_peek_from_isr_failed: tstamp:83749619126 queue:0x0b4b4500
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kworker/5:1-8029 [005] .... 2668.435022: rtos_queue_send_from_isr_failed: tstamp:83754155047 queue:0x0b4ae518
kworker/5:1-8029 [005] .... 2668.435025: rtos_queue_send_from_isr_failed: tstamp:83754155185 queue:0x0b4af2d8
kworker/5:1-8029 [005] .... 2668.435027: rtos_queue_send_from_isr_failed: tstamp:83754155321 queue:0x0b4b0098
kworker/5:1-8029 [005] .... 2668.435030: rtos_queue_send_from_isr_failed: tstamp:83754155458 queue:0x0b4b0e58
kworker/5:1-8029 [005] .... 2668.435032: rtos_queue_send_from_isr_failed: tstamp:83754155596 queue:0x0b4b1c18
kworker/5:1-8029 [005] .... 2668.435034: rtos_queue_send_failed: tstamp:83754156988 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2668.435038: rtos_queue_peek_from_isr_failed: tstamp:83754619109 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2668.602870: rtos_queue_peek_from_isr_failed: tstamp:83759619116 queue:0x0b4b4500
kworker/5:1-8029 [005] .... 2668.658976: rtos_queue_send_from_isr_failed: tstamp:83761009367 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2668.658985: rtos_queue_send_from_isr_failed: tstamp:83761009508 queue:0x0b4aad68
kworker/5:1-8029 [005] .... 2668.658987: rtos_queue_send_from_isr_failed: tstamp:83761009650 queue:0x0b4ac998
kworker/5:1-8029 [005] .... 2668.658989: rtos_queue_send_from_isr_failed: tstamp:83761009788 queue:0x0b4ae518
kworker/5:1-8029 [005] .... 2668.658991: rtos_queue_send_from_isr_failed: tstamp:83761009926 queue:0x0b4af2d8
kworker/5:1-8029 [005] .... 2668.658993: rtos_queue_send_from_isr_failed: tstamp:83761010063 queue:0x0b4b0098
kworker/5:1-8029 [005] .... 2668.658995: rtos_queue_send_from_isr_failed: tstamp:83761010201 queue:0x0b4b0e58
kworker/5:1-8029 [005] .... 2668.658997: rtos_queue_send_from_isr_failed: tstamp:83761010338 queue:0x0b4b1c18
kworker/5:1-8029 [005] .... 2668.659000: rtos_queue_send_failed: tstamp:83761011071 queue:0x0b4a7258
kworker/5:1-8029 [005] .... 2668.659002: rtos_queue_send_from_isr_failed: tstamp:83761014240 queue:0x0b4a7258
Can it help?
hello alfredosalvarani,
according to VI tracing logs, there’s no related registers messages, which means there’s no sensor signal sending to VI engine.
you should see tracing logs with registers reporting, such as CSIMUX_FRAME, CHANSEL_PXL_SOF, CHANSEL_PXL_EOF…etc
you might review the power-on sequence to ensure your bridge device works correctly.
please probe the MIPI signaling to check from the hardware side, or you might enable test-pattern-mode to generate pseudo CSI signaling for hardware connection verification.
thanks
Hello Jerry.
I think the bridge is on, I’ve measured the XTAL signals when I launch the gstreaming and there’s clock on chip. Also I’ve measured the CSI clock and CSI signal and there is something there. I’ll double check it whit a better oscilloscope.
Can you check if I’m configuring the VI engine (on BT) correctly, according with my hardware? (CSI ports, etc) I’m sending the schematic from this connection (ADV7280m to TX2).
Thanks
Hello Jerry.
I’ve measured the signals with a 1GHz oscilloscope and I’m sending the waves to you.
The CSI2 signal looks very good, I can see the low-power and the hi-speed parts, and when I zooming the signal the hi-speed bits looks very good, they are differential but I’m getting as a single, TX2 “see” it as differential and the quality will be very better, so I think there’s no problem to TX2 get this signal.
I’m sending the CSI2 clock waves too.
When I was measuring the signals, I try to cover the camera lens (There’s a analog camera plugged on ADV7280M input) and I can see that the bits pattern (hi speed) change. Also when I unplug or turn off the camera the signal change a lot (it turn in a very repetitive pattern suggesting a “black screen”)
Check the attached images, please.
Thinking about what the problem with VI engine, I’m wondering if I’m setting the correct CSI port on DT:
vi@15700000 {
num-channels = <1>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
status = "okay";
reg = <0>;
adv7280m_vi_in0: endpoint {
status = "okay";
port-index = <0>;
bus-width = <1>;
remote-endpoint = <&adv7280m_csi_out0>;
};
};
};
};
Is the lines
port-index = <0>;
bus-width = <1>;
means that I’m injecting the signal on CSI0_D0+ and CSI0_D0- pins with 1x lines?
Thanks!
hello alfredosalvarani,
port-index = <0>; bus-width = <1>;
these means enable CSI-A for 1-lane configuration to receive sensor signaling.
Hello Jerry.
ADV7280M is configured to automatic generate a “color pattern” when no camera is connected, so, when I disconect the camera a pattern is generated. I’m working to change this pattern to “color bars”.
thanks.
hello alfredosalvarani,
edit: TX2 did not working with rtcpu firmware.
if you’re based-on l4t-r32.2, you could also update rtcpu firmware to enable information dumps.
please backup and replace $OUT/Linux_for_Tegra/bootloader/camera-rtcpu-rce.img with the attachment, Debug_rtcpu.tar.gz
you’ll need to perform partition updates as following, $ sudo ./flash.sh -r -k rce-fw jetson-xavier mmcblk0p1
BTW,
could you please have kernel update to apply changes to correct VI streaming sequence, Topic 1050432.
thanks
Hello Jerry
I’ve applied the patch and same results here.
Do you have any other suggestion?
thanks
hello alfredosalvarani,
according to your previous comment #33, it has validate the port binding in sensor device tree was correct.
when you connect a camera, it’s bridge driver behavior to convert sensor signaling.
you may debug into bridge driver to check it has process sensor stream correctly.
thanks
Hello Jerry.
Maybe you misunderstood that I said: According to ADV’s user manual when there’s no camera present, it generate a pattern. BUT TX2 can’t get this too, exactly TX2 can’t get the image when a camera is present.
I tried to put a 20ms delay on tegra_channel_capture_frame function like on this topic: https://devtalk.nvidia.com/default/topic/1032730/jetson-tx2/adv7280m-error-pxl_sof-syncpt-timeout-/post/5254339/
But I can’t see any image, even a black scren… only the same old log:
[55699.011567] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[55699.018050] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[55699.251576] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[55699.258059] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
Do you know if there’s an away to know if any CSI signal is present on VI engine input?
Thanks
Hello Jerry,
Maybe I got two more bugs on NVidia code on file channel.c:
look at this function of channel.c:
static void tegra_channel_fmts_bitmap_init(struct tegra_channel *chan)
{
int ret, pixel_format_index = 0, init_code = 0;
struct v4l2_subdev *subdev = chan->subdev_on_csi;
struct v4l2_subdev_format fmt = {};
struct v4l2_subdev_mbus_code_enum code = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
bitmap_zero(chan->fmts_bitmap, MAX_FORMAT_NUM);
/*
* Initialize all the formats available from
* the sub-device and extract the corresponding
* index from the pre-defined video formats and initialize
* the channel default format with the active code
* Index zero as the only sub-device is sensor
*/
while (1) {
ret = v4l2_subdev_call(subdev, pad, enum_mbus_code,
NULL, &code);
if (ret < 0)
/* no more formats */
break;
pixel_format_index =
tegra_core_get_idx_by_code(chan, code.code, 0);
while (pixel_format_index >= 0) {
bitmap_set(chan->fmts_bitmap, pixel_format_index, 1);
/* Set init_code to the first matched format */
if (!init_code)
init_code = code.code;
/* Look for other formats with the same mbus code */
pixel_format_index = tegra_core_get_idx_by_code(chan,
code.code, pixel_format_index + 1);
}
code.index++;
}
if (!init_code) {
pixel_format_index =
tegra_core_get_idx_by_code(chan, TEGRA_VF_DEF, 0);
if (pixel_format_index >= 0) {
bitmap_set(chan->fmts_bitmap, pixel_format_index, 1);
init_code = TEGRA_VF_DEF;
}
}
/* Get the format based on active code of the sub-device */
ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt);
if (ret)
return;
/* Initiate the channel format to the first matched format */
chan->fmtinfo =
tegra_core_get_format_by_code(chan, fmt.format.code, 0);
v4l2_fill_pix_format(&chan->format, &fmt.format);
tegra_channel_update_format(chan, chan->format.width,
chan->format.height,
chan->fmtinfo->fourcc,
&chan->fmtinfo->bpp, 0);
if (chan->total_ports > 1)
update_gang_mode(chan);
}
At line 50 it will call the function linked on struct v4l2_subdev_pad_ops by member get_fmt.
This struct is defined on file media/v4l2-subdev.h of linux kernel code:
struct v4l2_subdev_pad_ops {
//suppressed code...
int (*get_fmt)(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format);
int (*set_fmt)(struct v4l2_subdev *sd,
struct v4l2_subdev_pad_config *cfg,
struct v4l2_subdev_format *format);
//suppressed code.
};
The second argument is of kind v4l2_subdev_pad_config, and at line 50 nvidia code send a NULL to this argument.
But on the file media/v4l2-subdev.h we have the definition and a comment about this type:
/**
* struct v4l2_subdev_pad_config - Used for storing subdev pad information.
*
* @try_fmt: &struct v4l2_mbus_framefmt
* @try_crop: &struct v4l2_rect to be used for crop
* @try_compose: &struct v4l2_rect to be used for compose
*
* This structure only needs to be passed to the pad op if the 'which' field
* of the main argument is set to %V4L2_SUBDEV_FORMAT_TRY. For
* %V4L2_SUBDEV_FORMAT_ACTIVE it is safe to pass %NULL.
*/
struct v4l2_subdev_pad_config {
struct v4l2_mbus_framefmt try_fmt;
struct v4l2_rect try_crop;
struct v4l2_rect try_compose;
};
The problem here is the initialization of the third argument (on line 5) because V4L2 library define
V4L2_SUBDEV_FORMAT_TRY = 0, so the variable fmt.which is V4L2_SUBDEV_FORMAT_TRY when get_fmt is called with cfg = NULL and this is not allowed by V4L2 library “This structure only needs to be passed to the pad op if the ‘which’ field of the main argument is set to V4L2_SUBDEV_FORMAT_TRY. For V4L2_SUBDEV_FORMAT_ACTIVE it is safe to pass NULL.”
Because of this the driver adv7180.c (and I supose many others) on Linux upstream code fail on initialization if used with NVidia L4T.
I changed the line 5 to:
struct v4l2_subdev_format fmt = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
And it doesn’t fail at driver initialization anymore.
Second bug
Now the problem is on function tegra_channel_set_format:
static int
tegra_channel_set_format(struct file *file, void *fh,
struct v4l2_format *format)
{
struct v4l2_fh *vfh = file->private_data;
struct tegra_channel *chan = to_tegra_channel(vfh->vdev);
int ret = 0;
/* get the suppod format by try_fmt */
ret = __tegra_channel_try_format(chan, &format->fmt.pix);
if (ret)
return ret;
if (vb2_is_busy(&chan->queue))
return -EBUSY;
return __tegra_channel_set_format(chan, &format->fmt.pix);
}
This function try to set the format by a “format try” on line 10, and if it don’t successful set
it by format active on line 17.
But on line 10 it calls the subfunction __tegra_channel_try_format
static int
__tegra_channel_try_format(struct tegra_channel *chan,
struct v4l2_pix_format *pix)
{
const struct tegra_video_format *vfmt;
struct v4l2_subdev_format fmt;
struct v4l2_subdev *sd = chan->subdev_on_csi;
int ret = 0;
/* Use the channel format if pixformat is not supported */
vfmt = tegra_core_get_format_by_fourcc(chan, pix->pixelformat);
if (!vfmt) {
pix->pixelformat = chan->format.pixelformat;
vfmt = tegra_core_get_format_by_fourcc(chan, pix->pixelformat);
}
fmt.which = V4L2_SUBDEV_FORMAT_TRY;
fmt.pad = 0;
v4l2_fill_mbus_format(&fmt.format, pix, vfmt->code);
ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &fmt);
if (ret == -ENOIOCTLCMD)
return -ENOTTY;
v4l2_fill_pix_format(pix, &fmt.format);
tegra_channel_set_bytesperline(chan, vfmt, pix);
tegra_channel_fmt_align(chan, vfmt,
&pix->width, &pix->height, &pix->bytesperline);
pix->sizeimage = get_aligned_buffer_size(chan,
pix->bytesperline, pix->height);
if (chan->fmtinfo->fourcc == V4L2_PIX_FMT_NV16)
pix->sizeimage *= 2;
return ret;
}
This function on line 21 calls the function “set_fmt” of driver and send a cfg=NULL like the previus bug.
I don’t have a solution to this second bug, so I did a workaround on the drivers source, and on “set_fmt” function if the cfg=NULL I return a ENOIOCTLCMD error, and the tegra source will call the driver function again with fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE
I looked at linux kernel drivers media/i2c/ and found others drivers that will fail with this tegra code. So maybe a good ideia to fix it.
's
hello alfredosalvarani,
according to below, it looks promising since now the VI engine is active.
PXL_SOF syncpt timeout! err = -11
VI engine allocate the buffers from the DT settings, and it expect the sensor streaming follow those settings.
there’s syncpt to sync with camera hardware analog signal with the software capture buffers.
that timeout failure means VI engine cannot receive start-of-frame signaling.
please ensure the sending packets following with SOF/EOF/SOF…EOF.
if there’s additional info, you’ll need to specify embedded_metadata_height to exclude it with actual signaling.
some materials for your reference,
you may check developer guide for Debugging Tips,
there’s also elinux page for camera bring-up. https://elinux.org/Jetson_TX2_Camera_BringUp
BTW,
thanks for point-out these two driver issue in comment #38.
Hi Jerry.
I can’t include the node mode0 on dt (under node adv7280m@21), if I try, tegra code crashs. And I can’t find why.
I’m trying to put this information on DT:
i2c@31c0000 {
adv7280m@21 {
/* Sensor Model */
sensor_model ="adv7280m";
devnode ="video0";
compatible = "adi,adv7280-m";
reg = <0x21>;
mclk = "extperiph1";
refclk_hz = <28636363>;
physical_w = "4.713";
physical_h = "3.494";
mode0 {
mclk_khz = "28636";
num_lanes = "1";
tegra_sinterface = "serial_a";
phy_mode = "DPHY";
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
dynamic_pixel_bit_depth = "16";
csi_pixel_bit_depth = "16";
mode_type = "yuv";
pixel_phase = "uyvy";
active_w = "720";
active_h = "576";
readout_orientation = "0";
line_length = "2200";
inherent_gain = "1";
mclk_multiplier = "2";
pix_clk_hz = "74250000";
gain_factor = "10";
min_gain_val = "0"; /* 0dB */
max_gain_val = "480"; /* 48dB */
step_gain_val = "3"; /* 0.3 */
default_gain = "0";
min_hdr_ratio = "1";
max_hdr_ratio = "1";
framerate_factor = "1000000";
min_framerate = "1500000";
max_framerate = "30000000"; /* 30 */
min_exp_time = "30"; /* us */
max_exp_time = "660000"; /* us */
step_exp_time = "1";
default_exp_time = "33334"; /* us */
embedded_metadata_height = "1";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7280m_out0: endpoint {
port-index = <0>;
bus-width = <1>;
remote-endpoint = <&adv7280m_csi_in0>;
};
};
};
};
};
On boot the crash is:
[ 10.001499] Internal error: Accessing user space memory outside uaccess.h routines: 96000005 [#1] PREEMPT SMP
[ 10.012966] Modules linked in: adv7280(+) nvgpu bluedroid_pm ip_tables x_tables
[ 10.021809] CPU: 0 PID: 3962 Comm: systemd-udevd Not tainted 4.9.140-tegra #22
[ 10.030421] Hardware name: quill (DT)
[ 10.035416] task: ffffffc1d85f4600 task.stack: ffffffc1d8750000
[ 10.042679] PC is at tegra_channel_init_subdevices+0x578/0x7a8
[ 10.042681] LR is at tegra_channel_init_subdevices+0x4d8/0x7a8
[ 10.042683] pc : [<ffffff8008b12d48>] lr : [<ffffff8008b12ca8>] pstate: 20400045
[ 10.042684] sp : ffffffc1d8753830
[ 10.042687] x29: ffffffc1d8753830 x28: ffffffc1d84fa000
[ 10.042690] x27: ffffffc1dc774000 x26: 0000000000000000
[ 10.042692] x25: 0000000000000000 x24: 0000000000000048
[ 10.042694] x23: ffffffc1e3111c58 x22: 0000000000000001
[ 10.042696] x21: 0000000000000000 x20: ffffff800903b000
[ 10.042698] x19: ffffffc1eb4c8018 x18: 0000000000000001
[ 10.042700] x17: 0000000000000001 x16: 0000000000000000
[ 10.042702] x15: ffffffffffffffff x14: ffffffc1d8753830
[ 10.042704] x13: ffffffc1d8753735 x12: ffffffffffffffff
[ 10.042706] x11: ffffffc1d87536f0 x10: ffffffc1d87536f0
[ 10.042708] x9 : ffffffc1eb5040d0 x8 : ffffffc1eb504000
[ 10.042710] x7 : ffffffc1d84fb000 x6 : 0000000000000090
[ 10.042712] x5 : 000000000000008d x4 : 0000000000000001
[ 10.042714] x3 : 0000000000000005 x2 : 0000000000000088
[ 10.042716] x1 : 0000000000000088 x0 : 0000000000000150
[ 10.042719] Process systemd-udevd (pid: 3962, stack limit = 0xffffffc1d8750000)
[ 10.042720] Call trace:
[ 10.042724] [<ffffff8008b12d48>] tegra_channel_init_subdevices+0x578/0x7a8
[ 10.042726] [<ffffff8008b13ae0>] tegra_vi_graph_notify_complete+0x328/0x6d8
[ 10.042731] [<ffffff8008af74a4>] v4l2_async_test_notify+0x104/0x120
[ 10.042733] [<ffffff8008af76e0>] v4l2_async_register_subdev+0x88/0x100
[ 10.042744] [<ffffff800118d060>] adv7180_probe+0x2f0/0x408 [adv7280]
[ 10.042747] [<ffffff8008acf814>] i2c_device_probe+0x144/0x258
[ 10.042751] [<ffffff800876ceb0>] driver_probe_device+0xd8/0x408
[ 10.042753] [<ffffff800876d2bc>] __driver_attach+0xdc/0x128
[ 10.042756] [<ffffff800876a92c>] bus_for_each_dev+0x5c/0xa8
[ 10.042757] [<ffffff800876c6b0>] driver_attach+0x30/0x40
[ 10.042759] [<ffffff800876c0e4>] bus_add_driver+0x20c/0x2a8
[ 10.042761] [<ffffff800876e1f4>] driver_register+0x6c/0x110
[ 10.042763] [<ffffff8008acff04>] i2c_register_driver+0x4c/0xb0
[ 10.042770] [<ffffff8001193018>] adv7180_driver_init+0x18/0x30 [adv7280]
[ 10.042773] [<ffffff8008083afc>] do_one_initcall+0x44/0x130
[ 10.042777] [<ffffff80081c2ddc>] do_init_module+0x64/0x1a8
[ 10.042781] [<ffffff80081581dc>] load_module+0x10a4/0x12d8
[ 10.042782] [<ffffff80081586c0>] SyS_finit_module+0xd8/0xf0
[ 10.042784] [<ffffff800808391c>] __sys_trace_return+0x0/0x4
[ 10.042788] ---[ end trace bc8d4484282d4aef ]---
And when I try to get image with gstreamer or v4l2-ctl, the crash is:
[ 160.179717] Internal error: Accessing user space memory outside uaccess.h routines: 96000005 [#2] PREEMPT SMP
[ 160.189634] Modules linked in: bnep fuse zram overlay bcmdhd cfg80211 adv7280(+) nvgpu bluedroid_pm ip_tables x_tables
[ 160.200496] CPU: 5 PID: 7851 Comm: v4l2src0:src Tainted: G D 4.9.140-tegra #22
[ 160.208852] Hardware name: quill (DT)
[ 160.212525] task: ffffffc179592a00 task.stack: ffffffc17282c000
[ 160.218438] PC is at vi4_channel_start_streaming+0x234/0x460
[ 160.224087] LR is at vi4_channel_start_streaming+0x1f4/0x460
[ 160.229739] pc : [<ffffff8008b17af4>] lr : [<ffffff8008b17ab4>] pstate: 20400145
[ 160.237126] sp : ffffffc17282fab0
[ 160.240440] x29: ffffffc17282fab0 x28: 0000000000000000
[ 160.245770] x27: ffffffc1eb4c8030 x26: 0000000000000001
[ 160.251107] x25: ffffff8009f81ca0 x24: 0000000000000012
[ 160.256454] x23: 0000000000000000 x22: ffffffc1eb4c8b58
[ 160.261798] x21: ffffffc1ead7b050 x20: ffffffc1eb0de820
[ 160.267143] x19: ffffffc1eb4c8018 x18: 0000000000000001
[ 160.272483] x17: 0000000000000002 x16: 0000000000000000
[ 160.277821] x15: ffffffffffffffff x14: ffffffc17282fab0
[ 160.283172] x13: ffffffc17282f9b5 x12: 0000000000000000
[ 160.288520] x11: ffffffc17282f970 x10: ffffffc17282f970
[ 160.293864] x9 : 0000000000000002 x8 : 0000000000000002
[ 160.299216] x7 : ffffff8008f96dc8 x6 : 0000000000000090
[ 160.304558] x5 : 000000000000008d x4 : 0000000000000001
[ 160.309901] x3 : 0000000000000000 x2 : 0000000000000150
[ 160.315252] x1 : 0000000000000150 x0 : 0000000000000000
[ 160.322115] Process v4l2src0:src (pid: 7851, stack limit = 0xffffffc17282c000)
[ 160.329344] Call trace:
[ 160.331817] [<ffffff8008b17af4>] vi4_channel_start_streaming+0x234/0x460
[ 160.338538] [<ffffff8008b0ed2c>] tegra_channel_start_streaming+0x3c/0x50
[ 160.345251] [<ffffff8008b06e2c>] vb2_start_streaming+0x6c/0x158
[ 160.351185] [<ffffff8008b08c04>] vb2_core_streamon+0x16c/0x1a0
[ 160.357032] [<ffffff8008b0b7c4>] vb2_streamon+0x54/0x88
[ 160.362270] [<ffffff8008b0b84c>] vb2_ioctl_streamon+0x54/0x60
[ 160.368033] [<ffffff8008ae5b54>] v4l_streamon+0x3c/0x50
[ 160.373274] [<ffffff8008aeab84>] __video_do_ioctl+0x204/0x2c8
[ 160.379032] [<ffffff8008aea530>] video_usercopy+0x2a0/0x6a0
[ 160.384617] [<ffffff8008aea96c>] video_ioctl2+0x3c/0x50
[ 160.389856] [<ffffff8008ae44a0>] v4l2_ioctl+0x88/0x118
[ 160.395013] [<ffffff8008273188>] do_vfs_ioctl+0xb0/0x8d8
[ 160.400336] [<ffffff8008273a3c>] SyS_ioctl+0x8c/0xa8
[ 160.405318] [<ffffff80080838c0>] el0_svc_naked+0x34/0x38
[ 160.410650] ---[ end trace bc8d4484282d4af0 ]---
if I remove mode0 node, there’s no crash.
But, some tips and configuration from links that you send me requere this node. Do you know why the tegra code crash it this node presente?
by the way, tc358840 don’t have this node on dt, and to avoid crash it’s implements tc358890_g_dv_timings function:
static struct v4l2_subdev_video_ops tc358840_subdev_video_ops = {
.g_input_status = tc358840_g_input_status,
.s_dv_timings = tc358840_s_dv_timings,
.g_dv_timings = tc358840_g_dv_timings,
.query_dv_timings = tc358840_query_dv_timings,
.g_mbus_config = tc358840_g_mbus_config,
.s_stream = tc358840_s_stream,
};
I think that this function supply the timing information to v4l2 and replace mode0 node on DT. But I have no ideia how to implement this on adv7280m (I made only a dummy function). Do you have any guide or tip how can I do this?
Thanks