ADV7280m Strcture Jetson Nano

[HT_MOB]

I am building software to control ADV7280m with v4l2 API with Jetson Nano developer kit.
I’m referring to the thread below, but the device file “video0” is not generated.

ADV7280m configuration

ADV7280m configuration

Hello In our custom board we have a ADV7280m (https://www.analog.com/en/products/adv7280.html) conected to a TX2 CSI 1-lane (See attached schematic). I want to configure the device tree and compile the driver, so I’ll can see the /dev/videoX and use it with gstreamer to capture imagens from a camera attached to this chip. I’m using the “NVIDIA Tegra Linux Driver Package (32.2)” on section “Sensor Software Driver Programming Guide”. I’v created the device tree on the end of the file tegra186-…

If you connect the camera module of imx219, video0 will be generated without any problem.
Therefore, I am trying to generate the device file of adv7280 by referring to the device driver and device tree of imx219.

How does imx219 dynamically generate video0?

As a result of reading the v4l2 document, it was written that / dev / video0 would be generated if video_device_register () was used, but that function is not written in the devioce driver of imx219.
Is video0 generated by a method other than video_device_register ()?

[ShaneCCC]

Should be the v4l2_async_register_subdev(sd) to gen the video node.
Have a reference to the tc358840.c

[HT_MOB]

Thank you for answering the question

When I implemented v4l2_async_register_subdev () in the adv7280 driver and checked the result, I found that this function returned 0 and no error occurred.

However, video0 is not generated.
What could be the cause?

I expect two points.
-The driver registration in udev is incorrect.
-There is an error in the construction of sd.

For udev, video0 is not generated with the following modifications.

/etc/udev/rules.d/99-tegra-devices.rules
The following is added.
KERNEL == “adv7 *” OWNER = “root” GROUP = “video” MODE = “0660”

[ShaneCCC]

You may need dig more to know the problem.

Also you may reference to below relative topic.

ADV7280m configuration

Hello In our custom board we have a ADV7280m (https://www.analog.com/en/products/adv7280.html) conected to a TX2 CSI 1-lane (See attached schematic). I want to configure the device tree and compile the driver, so I’ll can see the /dev/videoX and use it with gstreamer to capture imagens from a camera attached to this chip. I’m using the “NVIDIA Tegra Linux Driver Package (32.2)” on section “Sensor Software Driver Programming Guide”. I’v created the device tree on the end of the file tegra186-…

[HT_MOB]

I got a proven driver and device tree.

The file format of that device tree is dtsi format and I have never dealt with dtsi.

I used to be able to update the DT inside the Jetson Nano without using a Host Linux PC.
I edited “/boot/tegra210-p3448-0000-p3449-0000-b00.dts” and updated the DT using dtc.

Do I need a Host Linux PC to update the DT using the dtsi file?

[ShaneCCC]

You may need to build the dtb file from below document.

https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide/kernel_custom.html#

[HT_MOB]

Hi.

Thank you for teaching me.

I updated the DT and was able to get video0.

However, there are new problems.

When I execute the following command, an error occurs from dmesg and I cannot get the video.

$v4l2-ctl -d/dev/video0 --set-fmt-video width = 720, height = 576 --stream-mmap --stream-count=10 --stream-to=f20.raw

The content of the error is as shown in the image below.

What does this error 4000 mean?

What kind of solution do you have?

[ShaneCCC]

Enable the trace log for checking.

https://elinux.org/Jetson_TX2_Camera_BringUp

[HT_MOB]

Hi.

I have captured the trace log.
At first glance it looks like there are no errors, but can you find the error somewhere?

$v4l2-ctl -d /dev/video0 --set-fmt-video width=720,height=576 --stream-mmap --stream-count=10 --stream-to=f20.raw

root@jetson-desktop:~# cat /sys/kernel/debug/tracing/trace
tracer: nop

entries-in-buffer/entries-written: 154/154 #P:4

                          _-----=> irqs-off
                         / _----=> need-resched
                        | / _---=> hardirq/softirq
                        || / _--=> preempt-depth
                        ||| /     delay
       TASK-PID   CPU#  ||||    TIMESTAMP  FUNCTION
          | |       |   ||||       |         |
    v4l2-ctl-11441 [003] ....  2686.749031: tegra_channel_open: vi-output, adv7280 6-0021
    v4l2-ctl-11441 [000] ....  2686.752566: tegra_channel_set_power: adv7280 6-0021 : 0x1
    v4l2-ctl-11441 [000] ....  2686.756719: tegra_channel_set_power: nvcsi--1 : 0x1
    v4l2-ctl-11441 [000] ....  2686.756737: csi_s_power: enable : 0x1

vi-output, adv7-11442 [003] … 2686.766375: tegra_channel_set_stream: enable : 0x1
vi-output, adv7-11442 [003] … 2686.768438: tegra_channel_set_stream: nvcsi–1 : 0x1
vi-output, adv7-11442 [003] … 2686.768441: csi_s_stream: enable : 0x1
vi-output, adv7-11442 [003] … 2686.768473: tegra_channel_set_stream: adv7280 6-0021 : 0x1
vi-output, adv7-11442 [003] … 2686.788159: tegra_channel_capture_frame: sof:2686.635396787
vi-output, adv7-11442 [001] … 2686.809218: tegra_channel_capture_frame: sof:2686.655351318
vi-output, adv7-11442 [000] … 2686.828120: tegra_channel_capture_frame: sof:2686.675201266
vi-output, adv7-11442 [000] … 2686.848991: tegra_channel_capture_frame: sof:2686.695481214
vi-output, adv7-11442 [000] … 2686.868976: tegra_channel_capture_frame: sof:2686.715508453
vi-output, adv7-11442 [001] … 2686.890475: tegra_channel_capture_frame: sof:2686.735176110
vi-output, adv7-11442 [000] … 2686.908124: tegra_channel_capture_frame: sof:2686.755200693
vi-output, adv7-11442 [002] … 2686.929017: tegra_channel_capture_frame: sof:2686.775462933
vi-output, adv7-11442 [002] … 2686.948187: tegra_channel_capture_frame: sof:2686.795200328
vi-output, adv7-11442 [002] … 2686.968312: tegra_channel_capture_frame: sof:2686.815158558
vi-output, adv7-11442 [002] … 2686.988033: tegra_channel_capture_frame: sof:2686.835146110
vi-output, adv7-11442 [002] … 2687.008020: tegra_channel_capture_frame: sof:2686.855127724
vi-output, adv7-11442 [002] … 2687.028381: tegra_channel_capture_frame: sof:2686.875291422
vi-output, adv7-11442 [001] … 2687.050034: tegra_channel_capture_frame: sof:2686.895396995
vi-output, adv7-11442 [002] … 2687.068424: tegra_channel_capture_frame: sof:2686.915182151
vi-output, adv7-11442 [001] … 2687.088940: tegra_channel_capture_frame: sof:2686.935087151
vi-output, adv7-11442 [000] … 2687.108284: tegra_channel_capture_frame: sof:2686.955217985
vi-output, adv7-11442 [000] … 2687.128799: tegra_channel_capture_frame: sof:2686.975346995
vi-output, adv7-11442 [000] … 2687.148803: tegra_channel_capture_frame: sof:2686.995369912
vi-output, adv7-11442 [000] … 2687.168760: tegra_channel_capture_frame: sof:2687.15328610
vi-output, adv7-11442 [001] … 2687.190015: tegra_channel_capture_frame: sof:2687.35351057
vi-output, adv7-11442 [000] … 2687.208214: tegra_channel_capture_frame: sof:2687.55142203
vi-output, adv7-11442 [001] … 2687.229376: tegra_channel_capture_frame: sof:2687.75201110
vi-output, adv7-11442 [000] … 2687.247969: tegra_channel_capture_frame: sof:2687.95124339
vi-output, adv7-11442 [002] … 2687.270173: tegra_channel_capture_frame: sof:2687.115185120
vi-output, adv7-11442 [001] … 2687.289243: tegra_channel_capture_frame: sof:2687.135100537
vi-output, adv7-11442 [000] … 2687.308005: tegra_channel_capture_frame: sof:2687.155053193
vi-output, adv7-11442 [000] … 2687.328778: tegra_channel_capture_frame: sof:2687.175261578

trace_log.txt (15.3 KB)

[ShaneCCC]

Sorry didn’t aware it’s Nano platform the trace log didn’t for it.
Have enable the dev_dbg() in the csi2_fops.c to get the error status.

[HT_MOB]

Hi.

I enabled the dev_dbg() in the csi2_fops.c to get the error status.
The result is as follows.
Is the clock setting wrong?

Blockquote
[ 144.101112] adv7280: loading out-of-tree module taints kernel.
[ 144.108677] adv7280 6-0021: chip found @ 0x21 (Tegra I2C adapter)
[ 144.146891] vi 54080000.vi: subdev adv7280 6-0021 bound
[ 144.150732] adv7280 6-0021: adv7280-m probed!
[ 374.724829] single threaad enable !!!
[ 374.726487] vi 54080000.vi: cil_settingtime was autocalculated
[ 374.726493] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 374.732174] val1 : 16385
[ 374.732178] val2 : 16
[ 374.732182] val3 : 262144
[ 374.732189] vi 54080000.vi: tegra_channel_error_status:error 4000 frame 0
[ 374.740890] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00004015
[ 374.740945] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000000
[ 374.740995] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000000
[ 374.741781] vi 54080000.vi: cil_settingtime was autocalculated
[ 374.741786] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 374.741797] single threaad enable !!!
[ 374.747221] val1 : 16405
[ 374.747225] val2 : 16
[ 374.747227] val3 : 262208
[ 374.747233] vi 54080000.vi: tegra_channel_error_status:error 4000 frame 1
[ 374.754178] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00004015
[ 374.754184] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000000
[ 374.754189] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000000
[ 374.754234] vi 54080000.vi: cil_settingtime was autocalculated
[ 374.754239] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 374.754252] single threaad enable !!!
[ 374.762242] val1 : 16481
[ 374.762245] val2 : 16
[ 374.762248] val3 : 262208
[ 374.762253] vi 54080000.vi: tegra_channel_error_status:error 4000 frame 2
[ 374.769229] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 374.769235] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000000
[ 374.769240] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000000
[ 374.769284] vi 54080000.vi: cil_settingtime was autocalculated
[ 374.769288] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 374.769306] single threaad enable !!!
[ 374.777254] val1 : 16405
[ 374.777258] val2 : 16
[ 374.777261] val3 : 262208
[ 374.777268] vi 54080000.vi: tegra_channel_error_status:error 4000 frame 3
[ 374.784263] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00004015
[ 374.784269] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000000
[ 374.784275] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000000
[ 374.784322] vi 54080000.vi: cil_settingtime was autocalculated
[ 374.784330] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 374.784349] single threaad enable !!!
[ 374.892767] val1 : 16405
[ 374.892792] val2 : 16
[ 374.892808] val3 : 262208
[ 374.892858] vi 54080000.vi: tegra_channel_error_status:error 4000 frame 4
[ 374.900083] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00004015
[ 374.900097] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000000
[ 374.900110] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000000
[ 374.900219] vi 54080000.vi: cil_settingtime was autocalculated
[ 374.900237] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10

[ShaneCCC]

The REG CSI_CSI_PIXEL_PARSER_A_STATUS_0 show below error.

HPA_UNC_HDR_ERR: Uncorrectable Header Error. Set when header parser A parses a header with a
multi bit error. This error will be detected by the headers ECC, but can’t be corrected. The packet will be
discarded.

PPA_PL_CRC_ERR: PayLoad CRC Error. Set when a packet that was processed by PPA had a payload
CRC error.

PPA_SL_PROCESSED: Short Line Processed, Set when a line with a payload that is shorter than its
packet header word count is processed by PPA.

PPA_HDR_ERR_COR: Header Error Corrected, Set when a packet that was processed by PPA has a
single bit header error. This error will be detected by the headers ECC, and corrected by it if header error
correction is enabled (CSI_A_HEADER_EC_ENABLE = 0). This flag will be set and the packet will be
processed even if the error is not corrected

[HT_MOB]

Hi.

I’m sorry. I don’t understand why you explained CSI_CSI_PIXEL_PARSER_A_STATUS_0.

CSI_CSI_PIXEL_PARSER_A_STATUS_0 was not included in the error message.

Are CSI_CSI_PIXEL_PARSER_A_STATUS_0 related to TEGRA_CSI_PIXEL_PARSER_STATUS?

[ShaneCCC]

Yes, it is.

[HT_MOB]

Hi.

I read the source code of csi2_fops.c, vi2_fops.c, etc., but I couldn’t understand the relevance of CSI_CSI_PIXEL_PARSER_A_STATUS_0 and TEGRA_CSI_PIXEL_PARSER_STATUS.

Can you predict where the error is occurring?
For example, clock frequency, image size.

[ShaneCCC]

It’s could be the sensor output package or signal for the CRC error and PPA_HDR_ERR_COR.
The size incorrect for the short line.

[HT_MOB]

Hi.

What does short line mean?
Does it mean the height of the image size?

Where can I fix the short line?

[ShaneCCC]

It’s width of the resolution. You can try to modify the sensor driver to report less size to try.

[HT_MOB]

Hi.

The image size set by the sensor driver and the image sizes specified in the v4l2-ctl command match.

↓The test command
$v4l2-ctl -d /dev/video0 --set-fmt-video width=720,height=576 --stream-mmap --stream-count=10 --stream-to=f30.raw

↓part of the adv7280.c driver

static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
struct v4l2_mbus_framefmt *fmt)
{
struct adv7180_state *state = to_state(sd);

fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
fmt->width = 720;

if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) {
fmt->height /= 2;
}
fmt->height = 576; //for PAL
printk(“adv7280m: w=%d, h=%d\n”, fmt->width, fmt->height);

return 0;
}

Is there a driver other than these that specifies the image size?

[ShaneCCC]

You can try reduce the fmt->width = 720; and confirm by v4l2-ctl --list-formats-ext