Hello Shane
I changed the sensor_common.c to force signal->discontinuous_clk = 1:
/* initialize default if this prop not available */
// err = of_property_read_string(node, "discontinuous_clk", &temp_str);
// if (!err)
// signal->discontinuous_clk =
// !strncmp(temp_str, "yes", sizeof("yes"));
// else
signal->discontinuous_clk = 1;
printk(KERN_DEBUG "%s:%d signal->discontinuous_clk = %d\n",__FUNCTION__,__LINE__, signal->discontinuous_clk);
And I also, put a debug msg on top of the function:
static int sensor_common_parse_signal_props(
struct device *dev, struct device_node *node,
struct sensor_signal_properties *signal)
{
const char *temp_str;
int err = 0;
u32 value = 0;
u64 val64 = 0;
printk(KERN_DEBUG "%s:%d\n",__FUNCTION__,__LINE__);
But when I run the command:
v4l2-ctl --device /dev/video0 --stream-mmap --stream-to=frame.raw --stream-count=1
There’s no mention to sensor_common_parse_signal_props nor “signal->discontinuous_clk =”, so I think the function sensor_common_parse_signal_props is not called.
But I asked for more debug msg and got for csi.c the logs:
[ 504.479135] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=1
[ 504.479140] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 504.479149] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 504.479158] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[ 504.479161] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 504.479166] nvcsi 150c0000.nvcsi: no discontinuous_clk in of_node
[ 504.479168] nvcsi 150c0000.nvcsi: discontinuous_clk = 1 from of_node
[ 504.479170] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 504.479173] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 504.479178] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 504.479184] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 102
[ 504.479186] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 504.479189] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 25
I’ll try to change the function read_discontinuous_clk_from_dt from csi.c to force discontinuous_clk = 0
=== UPDATE ===
I’ve changed the csi.c function read_discontinuous_clk_from_dt to
u32 read_discontinuous_clk_from_dt(struct tegra_csi_channel *chan)
{
struct camera_common_data *s_data = chan->s_data;
struct sensor_mode_properties *mode = read_mode_from_dt(s_data);
struct device *dev = chan->csi->dev;
unsigned int discontinuous_clk = 0;
if (mode) {
discontinuous_clk = mode->signal_properties.discontinuous_clk;
dev_dbg(dev, "discontinuous_clk = %u reading from props\n", discontinuous_clk);
} else if (chan->of_node) {
int err = 0;
const char *str;
err = of_property_read_string(chan->of_node, "discontinuous_clk",
&str);
if (!err)
discontinuous_clk = !strncmp(str, "yes", sizeof("yes"));
else
dev_dbg(dev,
"no discontinuous_clk in of_node");
dev_dbg(dev, "discontinuous_clk = %u from of_node\n", discontinuous_clk);
}
return discontinuous_clk;
}
then, launch the command:
gst-launch-1.0 -v v4l2src ! 'video/x-raw, framerate=25/1' ! autovideosink
Dmesg log:
[ 1941.067625] to_state:443
[ 1941.067632] adv7280_s_power:530
[ 1941.067638] adv7280_set_power:498 on = 0
[ 1941.067644] I2C WRITE 24 @f
[ 1941.068097] I2C WRITE 80 @0
[ 1994.041506] adv7280_open:1528
[ 1994.041519] adv7280 6-0021: adv7280_open:
[ 1994.042957] to_state:443
[ 1994.042961] adv7280_s_power:530
[ 1994.042966] adv7280_set_power:498 on = 1
[ 1994.042969] I2C WRITE 4 @f
[ 1994.043137] I2C WRITE 2 @de
[ 1994.043284] I2C WRITE f7 @d2
[ 1994.043422] I2C WRITE 65 @d8
[ 1994.043555] I2C WRITE 9 @e0
[ 1994.043694] I2C WRITE 0 @2c
[ 1994.043827] I2C WRITE 80 @1d
[ 1994.043969] I2C WRITE 0 @0
[ 1994.045393] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 1994.045398] nvcsi 150c0000.nvcsi: csi_port: 0
[ 1994.045626] to_state:443
[ 1994.045629] adv7280_s_power:530
[ 1994.045632] adv7280_set_power:498 on = 0
[ 1994.045636] I2C WRITE 24 @f
[ 1994.045780] I2C WRITE 80 @0
[ 1994.108956] to_state:443
[ 1994.108963] adv7280_s_power:530
[ 1994.108968] adv7280_set_power:498 on = 1
[ 1994.108972] I2C WRITE 4 @f
[ 1994.109177] I2C WRITE 2 @de
[ 1994.109343] I2C WRITE f7 @d2
[ 1994.109489] I2C WRITE 65 @d8
[ 1994.109634] I2C WRITE 9 @e0
[ 1994.109797] I2C WRITE 0 @2c
[ 1994.109935] I2C WRITE 80 @1d
[ 1994.110071] I2C WRITE 0 @0
[ 1994.110273] to_state:443
[ 1994.110277] adv7280_g_input_status:451
[ 1994.110280] adv7280_read:324
[ 1994.110447] adv7280_read:324
[ 1994.110611] __adv7280_status:420 status1 = 0xd
[ 1994.110614] __adv7280_status:421 vid_sel = 0x4
[ 1994.110617] adv7280_status_to_v4l2:408
[ 1994.110619] status = 0
[ 1994.110622] RET = 0
[ 1994.110624] status = 0
[ 1994.111933] adv7280_enum_framesizes:1274
[ 1994.111960] tegra_channel_try_format:1876
[ 1994.111964] to_state:443
[ 1994.111968] adv7280_set_pad_format:893 format->which = 0
[ 1994.111970] adv7280_mbus_fmt:664
[ 1994.111974] adv7280_set_pad_format:921 FORMAT_TRY: format->format.code = 0x2006
[ 1994.111989] tegra_channel_try_format:1876
[ 1994.111992] to_state:443
[ 1994.111995] adv7280_set_pad_format:893 format->which = 0
[ 1994.111997] adv7280_mbus_fmt:664
[ 1994.112000] adv7280_set_pad_format:921 FORMAT_TRY: format->format.code = 0x2006
[ 1994.115276] to_state:443
[ 1994.115284] adv7280_s_power:530
[ 1994.115290] adv7280_set_power:498 on = 0
[ 1994.115297] I2C WRITE 24 @f
[ 1994.115498] I2C WRITE 80 @0
[ 2014.287099] adv7280_open:1528
[ 2014.287111] adv7280 6-0021: adv7280_open:
[ 2014.288585] to_state:443
[ 2014.288590] adv7280_s_power:530
[ 2014.288594] adv7280_set_power:498 on = 1
[ 2014.288597] I2C WRITE 4 @f
[ 2014.288766] I2C WRITE 2 @de
[ 2014.288913] I2C WRITE f7 @d2
[ 2014.289060] I2C WRITE 65 @d8
[ 2014.289195] I2C WRITE 9 @e0
[ 2014.289352] I2C WRITE 0 @2c
[ 2014.289561] I2C WRITE 80 @1d
[ 2014.289721] I2C WRITE 0 @0
[ 2014.291165] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 2014.291191] nvcsi 150c0000.nvcsi: csi_port: 0
[ 2014.291408] to_state:443
[ 2014.291412] adv7280_s_power:530
[ 2014.291415] adv7280_set_power:498 on = 0
[ 2014.291419] I2C WRITE 24 @f
[ 2014.291563] I2C WRITE 80 @0
[ 2014.355833] to_state:443
[ 2014.355840] adv7280_s_power:530
[ 2014.355844] adv7280_set_power:498 on = 1
[ 2014.355848] I2C WRITE 4 @f
[ 2014.356015] I2C WRITE 2 @de
[ 2014.356162] I2C WRITE f7 @d2
[ 2014.356307] I2C WRITE 65 @d8
[ 2014.356437] I2C WRITE 9 @e0
[ 2014.356563] I2C WRITE 0 @2c
[ 2014.356688] I2C WRITE 80 @1d
[ 2014.356824] I2C WRITE 0 @0
[ 2014.357007] to_state:443
[ 2014.357011] adv7280_g_input_status:451
[ 2014.357014] adv7280_read:324
[ 2014.357179] adv7280_read:324
[ 2014.357551] __adv7280_status:420 status1 = 0xd
[ 2014.357561] __adv7280_status:421 vid_sel = 0x4
[ 2014.357566] adv7280_status_to_v4l2:408
[ 2014.357571] status = 0
[ 2014.357575] RET = 0
[ 2014.357580] status = 0
[ 2014.359565] adv7280_enum_framesizes:1274
[ 2014.359590] tegra_channel_try_format:1876
[ 2014.359596] to_state:443
[ 2014.359600] adv7280_set_pad_format:893 format->which = 0
[ 2014.359603] adv7280_mbus_fmt:664
[ 2014.359610] adv7280_set_pad_format:921 FORMAT_TRY: format->format.code = 0x2006
[ 2014.359628] tegra_channel_try_format:1876
[ 2014.359631] to_state:443
[ 2014.359634] adv7280_set_pad_format:893 format->which = 0
[ 2014.359637] adv7280_mbus_fmt:664
[ 2014.359640] adv7280_set_pad_format:921 FORMAT_TRY: format->format.code = 0x2006
[ 2014.359944] tegra_channel_set_format:1926
[ 2014.359949] to_state:443
[ 2014.359952] adv7280_set_pad_format:893 format->which = 0
[ 2014.359955] adv7280_mbus_fmt:664
[ 2014.359959] adv7280_set_pad_format:921 FORMAT_TRY: format->format.code = 0x2006
[ 2014.359963] tegra_channel_set_format:1929 resultado try = 0
[ 2014.359966] tegra_channel_set_format:1933 postry = 0
[ 2014.359969] to_state:443
[ 2014.359971] adv7280_set_pad_format:893 format->which = 1
[ 2014.359974] adv7280_mbus_fmt:664
[ 2014.359977] adv7280_set_pad_format:911 FORMAT_ACTIVE: format->format.code = 0x2006
[ 2014.365386] tegra-vi4 15700000.vi: Create Surface with imgW=736, imgH=576, memFmt=203
[ 2014.387587] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=1
[ 2014.387596] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 2014.387607] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 2014.387618] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[ 2014.387643] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 2014.387649] nvcsi 150c0000.nvcsi: no discontinuous_clk in of_node
[ 2014.387654] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 2014.387658] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 2014.387662] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 2014.387669] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 2014.387677] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 102
[ 2014.387683] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 2014.387687] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 25
[ 2014.387695] to_state:443
[ 2014.387698] adv7280_s_stream:960
[ 2014.387701] adv7280_read:324
[ 2014.387894] adv7280_read:324
[ 2014.388058] __adv7280_status:420 status1 = 0xd
[ 2014.388061] __adv7280_status:421 vid_sel = 0x4
[ 2014.389042] video4linux video0: vi_notify_wait: vi4 got SOF syncpt buf[ffffffc1b63e4000]
[ 2014.389116] tegra-vi4 15700000.vi: Status: 4 channel:00 frame:0002
[ 2014.395554] tegra-vi4 15700000.vi: timestamp sof 2026109665920 eof 2026109692256 data 0x00000200
[ 2014.404806] tegra-vi4 15700000.vi: capture_id 5 stream 0 vchan 0
[ 2014.609427] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 2014.616094] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 2014.629760] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=1
[ 2014.629770] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 2014.629778] nvcsi 150c0000.nvcsi: no discontinuous_clk in of_node
[ 2014.629783] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 2014.629789] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 2014.629795] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 2014.629835] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000001
[ 2014.629845] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 2014.629860] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x00010000
[ 2014.638093] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x00010000
[ 2014.646395] nvcsi 150c0000.nvcsi: csi4_cil_check_status 397
[ 2014.646416] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=1
[ 2014.646428] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 2014.646447] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 2014.646466] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[ 2014.646531] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 2014.646545] nvcsi 150c0000.nvcsi: no discontinuous_clk in of_node
[ 2014.646556] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 2014.646568] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 2014.646578] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 2014.646592] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 2014.646609] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 102
[ 2014.646620] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 2014.646631] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 25
[ 2014.647170] tegra-vi4 15700000.vi: Create Surface with imgW=736, imgH=576, memFmt=203
[ 2014.647762] to_state:443
[ 2014.647776] adv7280_s_stream:960
[ 2014.647805] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=1
[ 2014.647822] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 2014.647840] nvcsi 150c0000.nvcsi: no discontinuous_clk in of_node
[ 2014.647853] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 2014.647865] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 2014.647878] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 2014.647895] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000001
[ 2014.647912] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 2014.647931] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x00000004
[ 2014.656861] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x00000004
[ 2014.664797] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x00000004
[ 2014.673058] nvcsi 150c0000.nvcsi: csi4_cil_check_status 397
[ 2014.682057] to_state:443
[ 2014.682065] adv7280_s_power:530
[ 2014.682069] adv7280_set_power:498 on = 0
[ 2014.682074] I2C WRITE 24 @f
[ 2014.682235] I2C WRITE 80 @0
and the command:
nvidia@nvidia-desktop:~$ v4l2-ctl --device /dev/video0 --stream-mmap --stream-to=frame.raw --stream-count=1
New timings found
VIDIOC_DQBUF: failed: Input/output error
DMESG results:
[ 2014.682057] to_state:443
[ 2014.682065] adv7280_s_power:530
[ 2014.682069] adv7280_set_power:498 on = 0
[ 2014.682074] I2C WRITE 24 @f
[ 2014.682235] I2C WRITE 80 @0
[ 2470.631932] to_state:443
[ 2470.631939] adv7280_s_power:530
[ 2470.631945] adv7280_set_power:498 on = 1
[ 2470.631949] I2C WRITE 4 @f
[ 2470.632110] I2C WRITE 2 @de
[ 2470.632256] I2C WRITE f7 @d2
[ 2470.632393] I2C WRITE 65 @d8
[ 2470.632527] I2C WRITE 9 @e0
[ 2470.632660] I2C WRITE 0 @2c
[ 2470.632794] I2C WRITE 80 @1d
[ 2470.632927] I2C WRITE 0 @0
[ 2470.634376] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 2470.634384] nvcsi 150c0000.nvcsi: csi_port: 0
[ 2470.635618] to_state:443
[ 2470.635623] adv7280_g_input_status:451
[ 2470.635627] adv7280_read:324
[ 2470.635818] adv7280_read:324
[ 2470.635986] __adv7280_status:420 status1 = 0xd
[ 2470.635990] __adv7280_status:421 vid_sel = 0x4
[ 2470.635993] adv7280_status_to_v4l2:408
[ 2470.635995] status = 0
[ 2470.635998] RET = 0
[ 2470.636000] status = 0
[ 2470.636041] adv7280_query_dv_timings:1189
[ 2470.636044] to_state:443
[ 2470.636047] adv7280_get_detected_timings:1055
[ 2470.636050] adv7280_read:324
[ 2470.636217] adv7280_read:324
[ 2470.636380] adv7280_read:324
[ 2470.636541] adv7280_read:324
[ 2470.636703] adv7280_get_detected_timings:1066 vid_sel = 0x04
[ 2470.636707] adv7280_get_detected_timings:1067 status1 = 0x0d
[ 2470.636710] adv7280_get_detected_timings:1068 status3 = 0x69
[ 2470.636721] adv7280_get_detected_timings:1069 autodetect = 0x7f
[ 2470.636743] DEBUG: interlaced = 1, width = 720, height = 960, vsync = 45, hsync = 138, pixelclock = 13513500
[ 2470.636748] adv7280 6-0021: adv7280_query_dv_timings: 720x960i30.0 (858x525)
[ 2470.636768] to_state:443
[ 2470.636773] adv7280_g_dv_timings:1039 state->timings = ffffffc1dde5ca6d
[ 2470.640964] tegra-vi4 15700000.vi: Create Surface with imgW=736, imgH=576, memFmt=203
[ 2470.662795] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=1
[ 2470.662801] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 2470.662811] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 2470.662820] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[ 2470.662823] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 2470.662828] nvcsi 150c0000.nvcsi: no discontinuous_clk in of_node
[ 2470.662830] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 2470.662833] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 2470.662835] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 2470.662840] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 2470.662847] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 102
[ 2470.662850] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 2470.662853] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 25
[ 2470.662859] to_state:443
[ 2470.662861] adv7280_s_stream:960
[ 2470.662864] adv7280_read:324
[ 2470.663023] adv7280_read:324
[ 2470.663181] __adv7280_status:420 status1 = 0xd
[ 2470.663184] __adv7280_status:421 vid_sel = 0x4
[ 2470.669849] video4linux video0: vi_notify_wait: vi4 got SOF syncpt buf[ffffffc1df440c00]
[ 2470.669877] tegra-vi4 15700000.vi: Status: 4 channel:00 frame:0002
[ 2470.676164] tegra-vi4 15700000.vi: timestamp sof 2482390528512 eof 2482390554848 data 0x00000200
[ 2470.685389] tegra-vi4 15700000.vi: capture_id 3 stream 0 vchan 0
[ 2470.890684] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 2470.897359] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 2470.907495] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=1
[ 2470.907522] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 2470.907547] nvcsi 150c0000.nvcsi: no discontinuous_clk in of_node
[ 2470.907558] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 2470.907568] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 2470.907577] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 2470.907679] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000001
[ 2470.907696] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 2470.907718] nvcsi 150c0000.nvcsi: csi4_cil_check_status 397
[ 2470.907749] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=1
[ 2470.907774] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 2470.907802] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 2470.907825] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[ 2470.907834] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 2470.907844] nvcsi 150c0000.nvcsi: no discontinuous_clk in of_node
[ 2470.907852] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 2470.907867] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 2470.907889] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 2470.907907] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 2470.907928] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 102
[ 2470.907947] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 2470.907969] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 25
[ 2470.910046] tegra-vi4 15700000.vi: Create Surface with imgW=736, imgH=576, memFmt=203
[ 2470.911922] to_state:443
[ 2470.911949] adv7280_s_stream:960
[ 2470.911989] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=1
[ 2470.912014] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 2470.912042] nvcsi 150c0000.nvcsi: no discontinuous_clk in of_node
[ 2470.912337] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 2470.912359] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 2470.912379] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 2470.912628] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000001
[ 2470.912644] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 2470.912658] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x00000004
[ 2470.921663] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x00000004
[ 2470.930714] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x00000004
[ 2470.939047] nvcsi 150c0000.nvcsi: csi4_cil_check_status 397
[ 2470.947489] to_state:443
[ 2470.947497] adv7280_s_power:530
[ 2470.947504] adv7280_set_power:498 on = 0
[ 2470.947512] I2C WRITE 24 @f
[ 2470.947716] I2C WRITE 80 @0
Now, I think SOF is gotten by VI, but another error happen, any ideia what error is?
Thanks
=== UPDATE 2 ===
Shane, debugging on csi.c, I can change the dt putting the discontinuos_clk=“no” on the place that csi.c can read:
host1x {
nvcsi@150c0000 {
num-channels = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
channel@0 {
reg = <0x0>;
status = "okay";
discontinuous_clk = "no";
ports {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
status = "okay";
reg = <0>;
adv7280m_csi_in0: endpoint@0 {
status = "okay";
port-index = <0>;
bus-width = <1>;
remote-endpoint = <&adv7280m_out0>;
};
};
port@1 {
status = "okay";
reg = <1>;
adv7280m_csi_out0: endpoint@1 {
status = "okay";
remote-endpoint = <&adv7280m_vi_in0>;
};
};
};
};
};
Now, with csi.c original file I can get the same results on dmesg:
[ 318.274578] tegra-vi4 15700000.vi: Create Surface with imgW=720, imgH=960, memFmt=203
[ 318.296504] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=1
[ 318.296511] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 318.296521] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 318.296529] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[ 318.296532] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 318.296538] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 318.296540] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 318.296542] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 318.296547] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 318.296554] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 102
[ 318.296557] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 318.296560] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 25
[ 318.296565] to_state:443
[ 318.296567] adv7280_s_stream:960
[ 318.296569] adv7280_read:324
[ 318.296726] adv7280_read:324
[ 318.296883] __adv7280_status:420 status1 = 0xd
[ 318.296886] __adv7280_status:421 vid_sel = 0x4
[ 318.299925] video4linux video0: vi_notify_wait: vi4 got SOF syncpt buf[ffffffc1b2718c00]
[ 318.316007] tegra-vi4 15700000.vi: Status: 7 channel:00 frame:0001
[ 318.322288] tegra-vi4 15700000.vi: timestamp sof 330026387328 eof 330042487328 data 0x00000001
[ 318.331349] tegra-vi4 15700000.vi: capture_id 1 stream 0 vchan 0
[ 318.526657] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 318.533288] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 318.544192] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=1
[ 318.544207] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 318.544232] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 318.544240] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 318.544248] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 318.544264] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000001
[ 318.544319] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 318.544339] nvcsi 150c0000.nvcsi: csi4_cil_check_status 397
[ 318.544354] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=1
[ 318.544362] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 318.544379] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 318.544394] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[ 318.544402] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 318.544410] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 318.544418] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 318.544425] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 318.544435] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 318.544448] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 102
[ 318.544456] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 318.544465] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 25
[ 318.545066] tegra-vi4 15700000.vi: Create Surface with imgW=720, imgH=960, memFmt=203
[ 318.545913] to_state:443
[ 318.545930] adv7280_s_stream:960
[ 318.545954] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=1
[ 318.545969] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 318.545989] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 318.546002] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 318.546016] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 318.546034] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000001
[ 318.546051] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 318.546070] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x00000008
[ 318.555214] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) INTR_STATUS 0x00000008
[ 318.564510] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERR_INTR_STATUS 0x00000008
[ 318.573294] nvcsi 150c0000.nvcsi: csi4_cil_check_status 397
[ 318.579481] to_state:443
[ 318.579488] adv7280_s_power:530
[ 318.579493] adv7280_set_power:498 on = 0
[ 318.579498] I2C WRITE 24 @f
[ 318.579683] I2C WRITE 80 @0
Is there any documentation saying how to setup the nvcsi@150c0000 node on dt? maybe the key to sincronize the ADV7280M output to NVCSI input is there.
Thanks