After update to R36.5, the gpio is fixed but uart in ttyTHS1 is not working in jetson orin nano baord

@KevinFFF

Hello All,
2 days ago I had problem with controlling a gpio in 40 pins header and after I fixed this issue with @KevinFFF by updating to R36.5 now I am facing a new issue that the UART in 40 pins header is not working anymore.
After many hours I discoverer the UART works in loopback but not works with other hardware, I need to link it with flight controller. Before the update it was working fine but now it is not working, I tried to use /dev/ttyTCU0 and it worked fine with my flight controller. the Problem I must use 2 uarts and I need the ttyTHS1 too.

I found few questions online but none of them with a fix only one suggested to use 20kohm resistor.

Please, I need urgent support. How to fix this problem now?

here is my dmesg:

[ 4825.845755] nvidia_smmu_context_fault_bank: 20 callbacks suppressed
[ 4825.845771] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xb3640000, fsynr=0x720011, cbfrsynra=0x404, cb=0
[ 4825.847870] tegra30_mc_handle_irq: 40 callbacks suppressed
[ 4825.847874] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff000x00000003ffffff00: VPR violation ((null))
[ 4825.847881] tegra-mc 2c00000.memory-controller: unkn@0x00000003ffffff00wn: secure write @0x00000003ffffff00: Route Sanity error ((null))
[ 4825.851782] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xb3640000, fsynr=0x720011, cbfrsynra=0x404, cb=0
[ 4825.853889] tegra-mc 2c00000.memor@0x00000003ffffff00-controller: unknown: secure write @0x00000003ffffff00: VPR violation ((null))
[ 4825.853893] tegr@0x00000003ffffff00-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: Route Sanity error ((null))
[ 4825.854216] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xb3640000, fsynr=0x720011, cbfrsynra=0x404, cb=0
[@0x00000003ffffff004825.856322] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: VPR vi@0x00000003ffffff00lation ((null))
[ 4825.856326] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: Route Sanity error ((null))
[ 4825.911845] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xb3640000, fsynr=0x720011, cbfrsynra=0x404, cb=0
[ 4825.914089] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xb3640000, fsy@0x00000003ffffff00r=0x720011, cbfrsynra=0x404, cb=0
[ 4825.914241] tegra-mc 2c00000.memory-controller: unknown: secu@0x00000003ffffff00e write @0x00000003ffffff00: VPR violation ((null))
[ 4825.914250] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: Route Sanity error ((null))
[ 4825.916166] arm-smmu 12000000.iommu: Unhandled context fa@0x00000003ffffff00lt: fsr=0x402, iova=0xb3640000, fsynr=0x720011, cbfrsynra=0x404, cb=0
[ 4825.918547] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: VPR violation ((null))
[ 4825.918553] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: Route Sanity error ((null))
[ 4825.935730] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xb3640000, fsynr=0x720011, cbfrsynra=0x404, cb=0
[ 4825.977730] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xb3640000, fsynr=0x720011, cbfrsynra=0x404, cb=0
[ 4826.013907] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xb3640000, fsynr=0x720011, cbfrsynra=0x404, cb=0
[ 4826.046754] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xb3640000, fsynr=0x720011, cbfrsynra=0x404, cb=0
[ 4830.911809] nvidia_smmu_context_fault_bank: 247 callbacks suppressed
[ 4830.911840] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xb3640000, fsynr=0x720011, cbfrsynra=0x404, cb=0

It is not the expected result to me as ttyTCU0 is the debug UART port which should be used as debug console/logs only.

The UART from 40-pins header should be /dev/ttyTHS1 with r36.x.
You can refer to https://elinux.org/Jetson/L4T/peripheral/#Mapping_3 for their mappings.

Please share the full dmesg as file for further check.

Do you enable HW flow control(i.e. RTS/CTS) in your case?

Hello @KevinFFF

It is not the expected result to me as ttyTCU0 is the debug UART port which should be used as debug console/logs only.

I have stopped the services of this uart so it does not send any debug info anymore and I am using it as communicate normal protocol since a while and it works fine as second uart.

The UART from 40-pins header should be /dev/ttyTHS1 with r36.x.
You can refer to https://elinux.org/Jetson/L4T/peripheral/#Mapping_3 for their mappings.

I am aware of this and have been using it normally with R36.4.

Do you enable HW flow control(i.e. RTS/CTS) in your case?

I tried both ways, and no difference make as I dont need any handshake but I tried cuz I thought it might be needed for the uart /dev/ttyTHS1 to be enabled. but as long as the loopback works fine when I use a jumper between TX and RX, this proves the UART already working.

Please share the full dmesg as file for further check.

Here is my dmesg as a full file I just booted up the jetson orin nano and tried to use the uart so, the dmesg gives you a clear idea, at the end of the file you find the UART missing packages.

dmesg_output.txt (71.1 KB)

**Have the uart /dev/ttyTHS1 in jetson orin nano 8gb dev board with R36.5 been tested and working fine?

Is there any work a round for now? I can’t proceed with my work without this uart, can I upgrade/update something so I make it works again?**

Here are some links for related issues might be better for you, some of them might be old but only for your reference:

Thank you for your support @KevinFFF

@KevinFFF
I have flashed new jetpack 6.2.2 and the same problem still exist, I used the SDKmanager for all the steps. Please, I need urgent support it has been 3 days many many hours wasted without any solution, I hope you can advice me with a solution.

What do you mean about “the UART missing packages” in dmesg?

[    2.164436] 3100000.serial: ttyTHS1 at MMIO 0x3100000 (irq = 112, base_baud = 0) is a TEGRA_UART

From the dmesg, UART1 is initialized as expected.

Do you have the scope or LA to measure the signal to compare the difference between loopback and connecting actual UART device?

What’s your UART device?
Are you using UART interface for RS485 use case?

Do you mean it works with R36.4 but not for R36.5?
If so, please also compare the device tree for these 2 releases.

Sorry, I waited for so long and I got tired of trying things. I had to do progress so I went back to R36.4 and I applied the patch for GPIO. So, my system is stable. You can close this thread without solution.

Okay, please let me know if you want to further debug the issue with R36.5.

Hi tahaalars94,

I have found the root cause of your UART issue after updating to r36.5.
Please refer to the following thread for the fix.
Solved: UART/Serial Port not working after upgradint to Jetpack 6.2.2 (Orin Nano/NX) - #7 by KevinFFF