Summary
On a Jetson Orin Nano Developer Kit (Super), freshly on L4T R39.2 / JetPack 7, I cannot get the 40-pin header UART (UART1 / /dev/ttyTHS1, pins 8/10) to transmit or receive. The controller probes cleanly, the pinmux reports function uarta at the register level, and the device-tree pad config is correct — but the TX pad (PR.02 / pin 8) never drives (measures ~0.3 V on a meter instead of idling at 3.3 V), and a TX↔RX hardware loopback returns no data at any baud.
This looks distinct from the known JetPack 6.2.2 DMA issue (Solved: UART/Serial Port not working after upgrading to JetPack 6.2.2) — I applied that fix (forced PIO) and the behavior is unchanged.
Question: Is ttyTHS1 on the 40-pin header functional on R39.2 for this board, and is there an additional pad/prod-setting required that jetson-io does not apply on R39?
Environment
# /etc/nv_tegra_release
# R39 (release), REVISION: 2.0, GCID: 45755727, BOARD: generic, EABI: aarch64, DATE: Mon Jun 1 09:28:48 PM UTC 2026
# KERNEL_VARIANT: oot
Model: NVIDIA Jetson Orin Nano Engineering Reference Developer Kit Super
Kernel: Linux 6.8.12-1021-tegra #1 SMP PREEMPT aarch64
TNSPEC: 3767-300-0005-T.1-1-1-jetson-orin-nano-devkit-super
Board: p3768-0000 + p3767-0005 (Orin Nano 8GB Super)
Console is on ttyTCU0 (USB-C debug). The 40-pin header UART is free (nvgetty inactive, nothing holds /dev/ttyTHS1).
Goal
Use the 40-pin header UART (pins 8 = UART1_TX, 10 = UART1_RX) as /dev/ttyTHS1 to talk to an external 3.3 V TTL device.
Steps taken
-
Enabled
uartaon the 40-pin header viajetson-io.
sudo /opt/nvidia/jetson-io/jetson-io.py→ Configure 40-pin Header → set pins 8/10 touarta→ Save and reboot. This created/boot/jetson-io-hdr40-user-custom.dtboand aJetsonIOentry inextlinux.conf(FDT+OVERLAYS), set asDEFAULT.
(Note: the headlessconfig-by-function.py -o dt uartaroute wrote a modified DTB but did not wire it into the boot chain — only the interactive tool added theOVERLAYSline. Possibly worth documenting.) -
Applied the known JetPack 6.2.2 DMA workaround (remove
dmas/dma-namesfromserial@3100000to force PIO). Confirmed in dmesg the UART now runs in PIO mode. No change to the symptom. -
Noticed
jetson-iosetnvidia,gpio-mode = <0x01>on both UART pins in the generated overlay — a property no other pin in the live tree carries. I rebuilt the overlay withgpio-mode = <0x00>. No change to the symptom.
Current state — everything checks out, pad still dead
dmesg — controller probes cleanly in PIO mode:
serial-tegra 3100000.serial: Adding to iommu group 1
serial-tegra 3100000.serial: RX in PIO mode
serial-tegra 3100000.serial: TX in PIO mode
3100000.serial: ttyTHS1 at MMIO 0x3100000 (irq = 133, base_baud = 0) is a TEGRA_UART
Pinmux register state (/sys/kernel/debug/pinctrl/*/pinmux-pins):
pin 110 (UART1_TX_PR2): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function uarta group uart1_tx_pr2
pin 111 (UART1_RX_PR3): 2430000.pinmux (GPIO UNCLAIMED) (HOG) function uarta group uart1_rx_pr3
Live device-tree pad config (dtc -I fs -O dts /proc/device-tree):
hdr40-pin8 { hdr40-pin10 {
nvidia,tristate = <0x00>; nvidia,tristate = <0x01>;
nvidia,function = "uarta"; nvidia,function = "uarta";
nvidia,enable-input = <0x00>; nvidia,enable-input = <0x01>;
nvidia,pins = "uart1_tx_pr2"; nvidia,pins = "uart1_rx_pr3";
nvidia,gpio-mode = <0x00>; nvidia,gpio-mode = <0x00>;
}; };
TX: drive enabled, input disabled. RX: input enabled, output tristated. Both function uarta. This is correct.
serial@3100000 node (live, post DMA-removal):
serial@3100000 {
iommus = <0x04 0x04>;
compatible = "nvidia,tegra194-hsuart";
status = "okay";
reg = <0x00 0x3100000 0x00 0x10000>;
...
};
Symptom / measurements
-
Loopback test: physical jumper across pins 8↔10 (continuity verified with a meter). Writing to
/dev/ttyTHS1and reading back returns nothing at 9600 and 57600:import serial, time s = serial.Serial("/dev/ttyTHS1", 57600, timeout=1) s.reset_input_buffer() s.write(b"PING"); s.flush(); time.sleep(0.2) print(repr(s.read(4))) # -> b'' -
Scope/meter on the TX pad (pin 8): while continuously streaming
0x55, pin 8 reads ~0.3 V (and pin 10, jumpered to it, the same). A live UART TX should idle at ~3.3 V and average ~1.5 V while streaming0x55. The pad appears to be floating / not driven, despitetristate=0andfunction uarta. -
The exact same external device + a CP2102 USB-TTL adapter works perfectly, so the device and my wiring are known-good.
What I’ve ruled out
- ❌ Wrong pin / miscount — pin 1 = 3.3 V, pin 2 = 5 V confirmed; jumper continuity on 8↔10 confirmed.
- ❌ Pinmux not applied —
pinmux-pinsshowsfunction uarta(HOG),GPIO UNCLAIMED. - ❌ Port held by getty/another process —
nvgettyinactive, no holders of/dev/ttyTHS1. - ❌ DMA fault (the 6.2.2 issue) — forced PIO mode, dmesg clean, no SMMU faults; no change.
- ❌
gpio-mode=1— set to 0; no change. - ❌ Permissions — user in
dialout, port opens fine.
Questions
- Is
UART1/ttyTHS1on the 40-pin header (pins 8/10) functional on R39.2 / JetPack 7 for the Orin Nano Super devkit (p3768-0000 + p3767-0005)? Has it been tested on this release? - With
function uarta,tristate=0,gpio-mode=0, and the HOG applied, why would the TX pad (PR.02) not drive? Is there an additional pad/prod setting (drive strength, pull, schmitt, or an MB1/prod-settings pinmux entry) thatjetson-io’shdr40overlay does not set on R39? - Is
jetson-ioemittingnvidia,gpio-mode = <0x01>for a UART function a known bug on R39? - Is the correct flashed pinmux (from the Orin Nano pinmux spreadsheet / MB1 BCT) required instead of a runtime overlay for UART1 to actually drive the pad on this release? If so, what is the recommended procedure on R39?
Happy to provide full dmesg, the generated .dtbo, or any register dumps. Thanks!