AGX Orin Timing from SYS_Vin_HV about to rise state to VDDin_PWR_BAD_N

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Orin
1

Hi AGX Orin developers,
I am looking for the timing from SYS_Vin_HV about to rise state to VDDin_PWR_BAD_N High state as AGX Orin design guide DG-10653-001_v1.1 | June 2022 depicts in Figure 5-2 on page 29.
I am also looking for the rise time of SYS_Vin_HV.
Thanks for your help.

3

Please check the carrier board schematic. The timing depends on SYS_VIN_HV voltage detector NCP301 design, the requirement is >0 and <300us per NCP301 datasheet.

There is no requirement for the rise time of SYS_VIN_HV.

4

Hi Ni6, on the carrier board SCH, the voltage input of NCP301 is VCC_SRC_FET, not VCC_SRC( used as SYS_VIN_HV). VDDin_PWR_BAD_N is used to monitor VCC_SRC_FET, not VCC_SRC. What is the timing delay between VCC_SRC_FET and VCC_SRC? And why does not the carrier board use NCP301(U69) monitor VCC_SRC?

5

Hi, please refer to this topic: VCC_SRC and VCC_SRC_FET on Orin Carrier board - #4 by Trumany

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