Audio I2S on 40 Pin Connector

Hi Jon,.

I have run the commands and I got the following output:

$ amixer -c tegrasndt210ref sset "ADMAIF1 Mux" "I2S4"
$ arecord -D hw:tegrasndt210ref,0 -r 16000 -f S16_LE -c 2 -d 10 test.wav &
$ sudo grep dap4 /sys/kernel/debug/tegra_pinctrl_reg
Bank: 1 Reg: 0x70003144 Val: 0x00000044 -> dap4_fs_pj4
Bank: 1 Reg: 0x70003148 Val: 0x00000044 -> dap4_din_pj5
Bank: 1 Reg: 0x7000314c Val: 0x00000044 -> dap4_dout_pj6
Bank: 1 Reg: 0x70003150 Val: 0x00000044 -> dap4_sclk_pj7
$ sudo grep "Name:\|J:\|BB:" /sys/kernel/debug/tegra_gpio
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
 J: 2:1 00 00 00 00 00 00 000000
BB: 6:3 01 00 00 00 00 00 000000
$ sudo cat /sys/kernel/debug/regmap/tegra210-i2s.3/registers
00: 00000000
04: 00000000
08: 00000000
0c: 00000002
10: 00000003
14: 00000003
18: 00000000
1c: 00000000
20: 03113300
24: 00000100
28: 00000000
2c: 00000000
30: 00000000
34: 00000000
38: 00000000
3c: 00000000
40: 00000001
44: 00000000
48: 00000000
4c: 00000003
50: 00000001
54: 00000003
58: 00000000
5c: 00000000
60: 00113300
64: 00000100
68: 00000000
6c: 00000000
70: 00000000
74: 00000000
78: 00000000
7c: 00000000
80: 00000001
84: 00000000
88: 00000001
8c: 00000000
90: 00000301
94: 00000000
98: 00000000
9c: 00000000
a0: 0f000403
a4: 0000000f
a8: 00000000
ac: 00000000
b0: 00000001

Btw, when arecord is not running, I get the following output:

00: 00000000
04: XXXXXXXX
08: 00000000
0c: XXXXXXXX
10: XXXXXXXX
14: 00000003
18: 00000000
1c: 00000000
20: 03113300
24: 00000100
28: 00000000
2c: 00000000
30: 00000000
34: 00000000
38: 00000000
3c: 00000000
40: 00000000
44: XXXXXXXX
48: 00000000
4c: XXXXXXXX
50: XXXXXXXX
54: 00000003
58: 00000000
5c: 00000000
60: 00113300
64: 00000100
68: 00000000
6c: 00000000
70: 00000000
74: 00000000
78: 00000000
7c: 00000000
80: 00000001
84: 00000000
88: 00000001
8c: 00000000
90: XXXXXXXX
94: 00000000
98: 00000000
9c: 00000000
a0: 0f000403
a4: 0000000f
a8: 00000000
ac: 00000000
b0: 00000001

Many thanks,

Kira

Hello Kira,

When arecord is not running, the I2S registered are not accessible directly and so the regmap driver will show the last known state for the registers. However, any registers that are marked as volatile will appear as XXXXXXXX. So what you are seeing when arecord is not running is expected.

Unfortunately, I am puzzled why this is not working for you at all. I am wondering if there is an issue with your board at this point. I am wondering if you could try using the Jetson-GPIO python scripts [0] to test the pins as GPIO to see if you can observe the pins toggling (please see below webpage for details on how to install and use). There is a ‘simple_out.py’ script that is included and by default toggles pin 12 on the 40-pin header which is the I2S_BCLK pin. If you are able to run this script and observe pin 12 toggling, you can then edit the script and update the ‘output_pin’ variable to be one of the other I2S pins. The mapping of I2S pins to the BCM pin numbering is …

I2S_SCLK → pin 12 → BCM 18
I2S_LRCK → pin 35 → BCM 19
I2S_DIN → pin 38 → BCM 20
I2S_DOUT → pin 40 → BCM 21

Regards,
Jon

[0] GitHub - NVIDIA/jetson-gpio: A Python library that enables the use of Jetson's GPIOs

Hi Kira,

Just to let you know that I have tested the I2S interface on the same version of the Jetson Nano (A02) that you have and it is working fine without anything connected. In other words, I see the bitclock and frame sync toggling at the expected frequencies. I have some adafruit i2s mems mics on order and so hopefully will have them next week to test.

I am still interested to see if you can see any of the pins toggle as GPIO. If they don’t we may need to see about exchanging your board.

I don’t suppose you would happen to have a 2nd Jetson Nano you can test?

Regards,
Jon

Hi Jon,

Thank you very much for your tips.

So, very interestingly, after installing Jetson.GPIO library, the pins and so the mic, started to work!

In summary, the steps that fixed the buggy configuration on my Jetson were:

  1. Flash Jetson Nano using SDK Manager (JetPack version 4.2) [host machine]

  2. Fix I2S configuration using DTB provided by @jas-mx above [host machine]

  1. Install Jetson.GPIO library [Jetson]
$ sudo apt update
$ sudo apt install python3-pip
$ pip3 --version
$ sudo pip3 install Jetson.GPIO

After installing Jetson.GPIO library, the I2S microphone starts to work!

I wonder if this solution is no longer needed with the recent release of JetPack 4.2.1…

Kira

Hi Kira,

Thanks for the feedback. I have received my microphones and will hopefully do some testing this week.

It is odd that installing the Jetson.GPIO library helped. It should not be needed in general. I will test with L4T r32.2 and let you know my findings.

Regards,
Jon

Hi Kira,

I have tested the Adafruit I2S MEMS mic on my Jetson Nano with rel32.2. To get the mic to work all I needed to do was force the pins to the I2S function by writing the following register using the U-Boot command line …

Tegra210 (P3450-Porg) # mw 0x6000d204 0

I am interested if this works for you with rel32.2.

Regards,
Jon

Hi Jon,

I have tested the command that you mentioned with JetPack 4.2.1 and, indeed, the microphone works straight away!

Now, I am trying to figure out how to make the fix permanent. Unfortunately, the DTB provided by @jas-mx no longer works with JetPack 4.2.1. If you have any suggestions on how to proceed, then please let me know.

Many thanks,

Kira

I’ll create a new dtb and post it, unfortunately the pins need to be mux’d correctly for a permanent fix.

Hi jas-mx,

That’s excellent - thank you very much. This is exactly what I need.

I’ll wait to hear from you.

Kind regards,

Kira

Hello!

An alternative to updating the DTB, is to rebuild the bootloader with the following change and flash the updated bootloader.

Regards,
Jon

Hi Jonathan

I’m trying to use RASPIAUDIO MIC+

I updated the pinmux, gpio and i made all the procedure to use the I2S4.

Really i can’t understand why didn’t work.
I solved the problem that i had initially with the NVIDIA LOGO and the system frozen.

The sound don’t work, but i2s4 apparentely is in operation.

Could you explain better in a new post what is the expected information to know that i2s4 connected with the alsamixer is working?

Best Regards

Hello!

First of once you have updated the pinmux you need to check that the pins are not configured as gpio. See …

Secondly, you need to check the pinmux configuration for dap4 looks good. You should have something like …

$ sudo grep dap4 /sys/kernel/debug/tegra_pinctrl_reg
Bank: 1 Reg: 0x70003144 Val: 0x00000044 -> dap4_fs_pj4
Bank: 1 Reg: 0x70003148 Val: 0x00000054 -> dap4_din_pj5
Bank: 1 Reg: 0x7000314c Val: 0x00000004 -> dap4_dout_pj6
Bank: 1 Reg: 0x70003150 Val: 0x00000044 -> dap4_sclk_pj7

Please note that the most important bit settings in the above are …

  1. bit[0:1] = 0x0 (mode is i2s)
  2. bit[4] = 0 (output enable, not necessary for din)
  3. bit[6] = 1 (input enable, not necessary for dout)

Then reset the mixer controls …

$ alsactl init tegrasndt210ref

Verify that I2S4 is mapped to the ADMAIF1 …

$ amixer -c tegrasndt210ref sget "ADMAIF1 Mux"
$ amixer -c tegrasndt210ref sget "I2S4 Mux"

Then you should be able to record/play from I2S4 …

$ arecord -D hw:tegrasndt210ref,0 -c <channels> -r <srate> -f <sample-size> cap.wav
$ aplay -D hw:tegrasndt210ref,0 cap.wav

I assume that the raspiaudio mic+ DAC/ADC does not require any configuration? In other words, there is no control interface (I2C/SPI) used to configure it?

Regards,
Jon

Hi

I want to try to explain all the process… With this configuration NO SOUND and i can execute arecord but only noise is in the test.wav verified copying to another computer.

First sharing my configuration files:

I flashed NANO with this PINMUX for u-boot:

/*

  • Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
  • SPDX-License-Identifier: GPL-2.0+
    */

/*

  • THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
  • To generate this file, use the tegra-pinmux-scripts tool available from
  • https://github.com/NVIDIA/tegra-pinmux-scripts
  • Run “board-to-uboot.py nano”.
  • Used the T210_P3448_SKU0_pinmux sheet, tab B00-B01 as of 2 May 2019, v18.
  • NOTE: To WAR A01 <-> A02 Porg differences, I’ve edited this file.
  •   Removed DAP1/DAP4 pinmux programming as a WAR for A01 Porg.
    
  • Also, A02 <-> B00/B01 diff includes CLK_32K_OUT, which is NC on A02,
  • and CC7/I1 muxes/GPIOs (both OUT1).
    */

#ifndef PINMUX_CONFIG_P3450_PORG_H
#define PINMUX_CONFIG_P3450_PORG_H

#define GPIO_INIT(_port, _gpio, _init)
{
.gpio = TEGRA_GPIO(_port, gpio),
.init = TEGRA_GPIO_INIT
##_init,
}

static const struct tegra_gpio_config p3450_porg_gpio_inits = {
/* port, pin, init_val */
GPIO_INIT(A, 5, IN),
GPIO_INIT(A, 6, OUT1),
GPIO_INIT(B, 4, IN),
GPIO_INIT(B, 5, IN),
GPIO_INIT(B, 6, IN),
GPIO_INIT(B, 7, IN),
GPIO_INIT(C, 0, IN),
GPIO_INIT(C, 1, IN),
GPIO_INIT(C, 2, IN),
GPIO_INIT(C, 3, IN),
GPIO_INIT(C, 4, IN),
GPIO_INIT(E, 6, IN),
GPIO_INIT(G, 2, IN),
GPIO_INIT(G, 3, IN),
GPIO_INIT(H, 0, OUT0),
GPIO_INIT(H, 2, IN),
GPIO_INIT(H, 3, OUT0),
GPIO_INIT(H, 4, OUT0),
GPIO_INIT(H, 5, IN),
GPIO_INIT(H, 6, IN),
GPIO_INIT(H, 7, OUT0),
GPIO_INIT(I, 0, OUT0),
GPIO_INIT(I, 1, OUT1),
GPIO_INIT(I, 2, OUT0),
GPIO_INIT(S, 5, IN),
GPIO_INIT(S, 7, OUT0),
GPIO_INIT(T, 0, OUT0),
GPIO_INIT(V, 0, IN),
GPIO_INIT(V, 1, IN),
GPIO_INIT(X, 3, OUT1),
GPIO_INIT(X, 4, IN),
GPIO_INIT(X, 5, IN),
GPIO_INIT(X, 6, IN),
GPIO_INIT(Y, 1, IN),
GPIO_INIT(Y, 2, IN),
GPIO_INIT(Z, 0, IN),
GPIO_INIT(Z, 2, IN),
GPIO_INIT(Z, 3, OUT0),
GPIO_INIT(CC, 4, IN),
GPIO_INIT(CC, 7, OUT1),
GPIO_INIT(DD, 0, IN),
};

#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, e_io_hv)
{
.pingrp = PMUX_PINGRP
##pingrp,
.func = PMUX_FUNC
##mux,
.pull = PMUX_PULL
##pull,
.tristate = PMUX_TRI
##tri,
.io = PMUX_PIN
##io,
.od = PMUX_PIN_OD
##od,
.e_io_hv = PMUX_PIN_E_IO_HV
##_e_io_hv,
.lock = PMUX_PIN_LOCK_DEFAULT,
}

static const struct pmux_pingrp_config p3450_porg_pingrps = {
/* pingrp, mux, pull, tri, e_input, od, e_io_hv */
PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PA6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI2_MOSI_PB4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SPI2_MISO_PB5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SPI2_SCK_PB6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SPI2_CS0_PB7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SPI1_MOSI_PC0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SPI1_MISO_PC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SPI1_SCK_PC2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SPI1_CS0_PC3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SPI1_CS1_PC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(UART3_RTS_PD3, UARTC, UP, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DMIC3_CLK_PE4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART2_RX_PG1, UARTB, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(UART2_RTS_PG2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(UART2_CTS_PG3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART4_CTS_PI7, UARTD, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM_AF_EN_PS5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART1_RX_PU1, UARTA, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(UART1_RTS_PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(UART1_CTS_PU3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(LCD_BL_PWM_PV0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(TOUCH_RST_PV6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(ALS_PROX_INT_PX3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(BUTTON_VOL_DOWN_PX7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(LCD_TE_PY2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(PZ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(AUD_MCLK_PBB0, AUD, UP, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(DVFS_CLK_PBB2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
PINCFG(HDMI_INT_DP_HPD_PCC1, DP, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(USB_VBUS_EN0_PCC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL),
PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
PINCFG(DP_HPD0_PCC6, DP, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
PINCFG(SPI2_CS1_PDD0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CPU_PWR_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(DAP4_FS_PJ4, I2S4B, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP4_DIN_PJ5, I2S4B, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(DAP4_DOUT_PJ6, I2S4B, DOWN, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(DAP4_SCLK_PJ7, I2S4B, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
};

#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, hsm)
{
.drvgrp = PMUX_DRVGRP
##_drvgrp,
.slwf = _slwf,
.slwr = _slwr,
.drvup = _drvup,
.drvdn = drvdn,
.lpmd = PMUX_LPMD
##lpmd,
.schmt = PMUX_SCHMT
##schmt,
.hsm = PMUX_HSM
##_hsm,
}

static const struct pmux_drvgrp_config p3450_porg_drvgrps = {
};

#endif /* PINMUX_CONFIG_P3450_PORG_H */

MY GPIO FOR THE CBOOT configuration in the DTSI files

/*This dtsi file was generated by T210_P3448_SKU0_pinmux.xlsm Revision: 9 /
/

  • Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
  • This program is free software; you can redistribute it and/or modify
  • it under the terms of the GNU General Public License as published by
  • the Free Software Foundation; either version 2 of the License, or
  • (at your option) any later version.
  • This program is distributed in the hope that it will be useful, but WITHOUT
  • ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  • FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  • more details.
  • You should have received a copy of the GNU General Public License along
  • with this program; if not, write to the Free Software Foundation, Inc.,
  • 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
    */

#include <dt-bindings/gpio/tegra-gpio.h>

/ {
gpio: gpio@6000d000 {
gpio-init-names = “default”;
gpio-init-0 = <&gpio_default>;

	gpio_default: default {
		gpio-input = <
			TEGRA_GPIO(B, 4)
			TEGRA_GPIO(B, 5)
			TEGRA_GPIO(B, 6)
			TEGRA_GPIO(B, 7)
			TEGRA_GPIO(DD, 0)
			TEGRA_GPIO(E, 6)
			TEGRA_GPIO(S, 5)
			TEGRA_GPIO(A, 5)
			TEGRA_GPIO(X, 4)
			TEGRA_GPIO(X, 5)
			TEGRA_GPIO(X, 6)
			TEGRA_GPIO(Y, 1)
			TEGRA_GPIO(Y, 2)
			TEGRA_GPIO(V, 0)
			TEGRA_GPIO(V, 1)
			TEGRA_GPIO(Z, 0)
			TEGRA_GPIO(Z, 2)
			TEGRA_GPIO(G, 2)
			TEGRA_GPIO(G, 3)
			TEGRA_GPIO(C, 0)
			TEGRA_GPIO(C, 1)
			TEGRA_GPIO(C, 2)
			TEGRA_GPIO(C, 3)
			TEGRA_GPIO(C, 4)
			TEGRA_GPIO(H, 2)
			TEGRA_GPIO(H, 5)
			TEGRA_GPIO(H, 6)
			TEGRA_GPIO(I, 1)
			TEGRA_GPIO(CC, 4)
			>;
		gpio-output-low = <
			TEGRA_GPIO(S, 7)
			TEGRA_GPIO(T, 0)
			TEGRA_GPIO(Z, 3)
			TEGRA_GPIO(H, 0)
			TEGRA_GPIO(H, 3)
			TEGRA_GPIO(H, 4)
			TEGRA_GPIO(H, 7)
			TEGRA_GPIO(I, 0)
			TEGRA_GPIO(I, 2)
			>;
		gpio-output-high = <
			TEGRA_GPIO(A, 6)
			TEGRA_GPIO(X, 3)
			>;
	};
};

};

Now my PINMUX files for the CBOOT configuration:

/*This dtsi file was generated by T210_P3448_SKU0_pinmux.xlsm Revision: 9 /
/

  • Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
  • This program is free software; you can redistribute it and/or modify
  • it under the terms of the GNU General Public License as published by
  • the Free Software Foundation; either version 2 of the License, or
  • (at your option) any later version.
  • This program is distributed in the hope that it will be useful, but WITHOUT
  • ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  • FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  • more details.
  • You should have received a copy of the GNU General Public License along
  • with this program; if not, write to the Free Software Foundation, Inc.,
  • 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
    */

#include <dt-bindings/pinctrl/pinctrl-tegra.h>

/ {
pinmux: pinmux@700008d4 {
status = “okay”;
pinctrl-names = “default”, “drive”, “unused”;
pinctrl-0 = <&pinmux_default>;
pinctrl-1 = <&drive_default>;
pinctrl-2 = <&pinmux_unused_lowpower>;

	pinmux_default: common {
		/* SFIO Pin Configuration */
		dvfs_pwm_pbb1 {
			nvidia,pins = "dvfs_pwm_pbb1";
			nvidia,function = "cldvfs";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		dmic1_clk_pe0 {
			nvidia,pins = "dmic1_clk_pe0";
			nvidia,function = "i2s3";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		dmic1_dat_pe1 {
			nvidia,pins = "dmic1_dat_pe1";
			nvidia,function = "i2s3";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		dmic2_clk_pe2 {
			nvidia,pins = "dmic2_clk_pe2";
			nvidia,function = "i2s3";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		dmic2_dat_pe3 {
			nvidia,pins = "dmic2_dat_pe3";
			nvidia,function = "i2s3";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		pe7 {
			nvidia,pins = "pe7";
			nvidia,function = "pwm3";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		gen3_i2c_scl_pf0 {
			nvidia,pins = "gen3_i2c_scl_pf0";
			nvidia,function = "i2c3";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
		};

		gen3_i2c_sda_pf1 {
			nvidia,pins = "gen3_i2c_sda_pf1";
			nvidia,function = "i2c3";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
		};

		cam_i2c_scl_ps2 {
			nvidia,pins = "cam_i2c_scl_ps2";
			nvidia,function = "i2cvi";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
		};

		cam_i2c_sda_ps3 {
			nvidia,pins = "cam_i2c_sda_ps3";
			nvidia,function = "i2cvi";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
		};

		cam1_mclk_ps0 {
			nvidia,pins = "cam1_mclk_ps0";
			nvidia,function = "extperiph3";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		cam2_mclk_ps1 {
			nvidia,pins = "cam2_mclk_ps1";
			nvidia,function = "extperiph3";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pex_l0_clkreq_n_pa1 {
			nvidia,pins = "pex_l0_clkreq_n_pa1";
			nvidia,function = "pe0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
		};

		pex_l0_rst_n_pa0 {
			nvidia,pins = "pex_l0_rst_n_pa0";
			nvidia,function = "pe0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
		};

		pex_l1_clkreq_n_pa4 {
			nvidia,pins = "pex_l1_clkreq_n_pa4";
			nvidia,function = "pe1";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
		};

		pex_l1_rst_n_pa3 {
			nvidia,pins = "pex_l1_rst_n_pa3";
			nvidia,function = "pe1";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
		};

		pex_wake_n_pa2 {
			nvidia,pins = "pex_wake_n_pa2";
			nvidia,function = "pe";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
		};

		sdmmc1_clk_pm0 {
			nvidia,pins = "sdmmc1_clk_pm0";
			nvidia,function = "sdmmc1";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		sdmmc1_cmd_pm1 {
			nvidia,pins = "sdmmc1_cmd_pm1";
			nvidia,function = "sdmmc1";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		sdmmc1_dat0_pm5 {
			nvidia,pins = "sdmmc1_dat0_pm5";
			nvidia,function = "sdmmc1";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		sdmmc1_dat1_pm4 {
			nvidia,pins = "sdmmc1_dat1_pm4";
			nvidia,function = "sdmmc1";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		sdmmc1_dat2_pm3 {
			nvidia,pins = "sdmmc1_dat2_pm3";
			nvidia,function = "sdmmc1";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		sdmmc1_dat3_pm2 {
			nvidia,pins = "sdmmc1_dat3_pm2";
			nvidia,function = "sdmmc1";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		sdmmc3_clk_pp0 {
			nvidia,pins = "sdmmc3_clk_pp0";
			nvidia,function = "sdmmc3";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		sdmmc3_cmd_pp1 {
			nvidia,pins = "sdmmc3_cmd_pp1";
			nvidia,function = "sdmmc3";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		sdmmc3_dat0_pp5 {
			nvidia,pins = "sdmmc3_dat0_pp5";
			nvidia,function = "sdmmc3";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		sdmmc3_dat1_pp4 {
			nvidia,pins = "sdmmc3_dat1_pp4";
			nvidia,function = "sdmmc3";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		sdmmc3_dat2_pp3 {
			nvidia,pins = "sdmmc3_dat2_pp3";
			nvidia,function = "sdmmc3";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		sdmmc3_dat3_pp2 {
			nvidia,pins = "sdmmc3_dat3_pp2";
			nvidia,function = "sdmmc3";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		shutdown {
			nvidia,pins = "shutdown";
			nvidia,function = "shutdown";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		lcd_gpio2_pv4 {
			nvidia,pins = "lcd_gpio2_pv4";
			nvidia,function = "pwm1";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pwr_i2c_scl_py3 {
			nvidia,pins = "pwr_i2c_scl_py3";
			nvidia,function = "i2cpmu";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
		};

		pwr_i2c_sda_py4 {
			nvidia,pins = "pwr_i2c_sda_py4";
			nvidia,function = "i2cpmu";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
		};

		clk_32k_in {
			nvidia,pins = "clk_32k_in";
			nvidia,function = "clk";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		pz1 {
			nvidia,pins = "pz1";
			nvidia,function = "sdmmc1";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		pz5 {
			nvidia,pins = "pz5";
			nvidia,function = "soc";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		core_pwr_req {
			nvidia,pins = "core_pwr_req";
			nvidia,function = "core";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pwr_int_n {
			nvidia,pins = "pwr_int_n";
			nvidia,function = "pmi";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		gen1_i2c_scl_pj1 {
			nvidia,pins = "gen1_i2c_scl_pj1";
			nvidia,function = "i2c1";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
		};

		gen1_i2c_sda_pj0 {
			nvidia,pins = "gen1_i2c_sda_pj0";
			nvidia,function = "i2c1";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
		};

		gen2_i2c_scl_pj2 {
			nvidia,pins = "gen2_i2c_scl_pj2";
			nvidia,function = "i2c2";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
		};

		gen2_i2c_sda_pj3 {
			nvidia,pins = "gen2_i2c_sda_pj3";
			nvidia,function = "i2c2";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
		};

		uart2_tx_pg0 {
			nvidia,pins = "uart2_tx_pg0";
			nvidia,function = "uartb";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		uart2_rx_pg1 {
			nvidia,pins = "uart2_rx_pg1";
			nvidia,function = "uartb";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		uart1_tx_pu0 {
			nvidia,pins = "uart1_tx_pu0";
			nvidia,function = "uarta";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		uart1_rx_pu1 {
			nvidia,pins = "uart1_rx_pu1";
			nvidia,function = "uarta";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		jtag_rtck {
			nvidia,pins = "jtag_rtck";
			nvidia,function = "jtag";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		uart3_tx_pd1 {
			nvidia,pins = "uart3_tx_pd1";
			nvidia,function = "uartc";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		uart3_rx_pd2 {
			nvidia,pins = "uart3_rx_pd2";
			nvidia,function = "uartc";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		uart3_rts_pd3 {
			nvidia,pins = "uart3_rts_pd3";
			nvidia,function = "uartc";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		uart3_cts_pd4 {
			nvidia,pins = "uart3_cts_pd4";
			nvidia,function = "uartc";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		uart4_tx_pi4 {
			nvidia,pins = "uart4_tx_pi4";
			nvidia,function = "uartd";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		uart4_rx_pi5 {
			nvidia,pins = "uart4_rx_pi5";
			nvidia,function = "uartd";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		uart4_rts_pi6 {
			nvidia,pins = "uart4_rts_pi6";
			nvidia,function = "uartd";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		uart4_cts_pi7 {
			nvidia,pins = "uart4_cts_pi7";
			nvidia,function = "uartd";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		qspi_io0_pee2 {
			nvidia,pins = "qspi_io0_pee2";
			nvidia,function = "qspi";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		qspi_io1_pee3 {
			nvidia,pins = "qspi_io1_pee3";
			nvidia,function = "qspi";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		qspi_sck_pee0 {
			nvidia,pins = "qspi_sck_pee0";
			nvidia,function = "qspi";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		qspi_cs_n_pee1 {
			nvidia,pins = "qspi_cs_n_pee1";
			nvidia,function = "qspi";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		qspi_io2_pee4 {
			nvidia,pins = "qspi_io2_pee4";
			nvidia,function = "qspi";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		qspi_io3_pee5 {
			nvidia,pins = "qspi_io3_pee5";
			nvidia,function = "qspi";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		dap2_din_paa2 {
			nvidia,pins = "dap2_din_paa2";
			nvidia,function = "i2s2";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		dap2_dout_paa3 {
			nvidia,pins = "dap2_dout_paa3";
			nvidia,function = "i2s2";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		dap2_fs_paa0 {
			nvidia,pins = "dap2_fs_paa0";
			nvidia,function = "i2s2";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		dap2_sclk_paa1 {
			nvidia,pins = "dap2_sclk_paa1";
			nvidia,function = "i2s2";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		dp_hpd0_pcc6 {
			nvidia,pins = "dp_hpd0_pcc6";
			nvidia,function = "dp";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		hdmi_int_dp_hpd_pcc1 {
			nvidia,pins = "hdmi_int_dp_hpd_pcc1";
			nvidia,function = "dp";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
		};

		hdmi_cec_pcc0 {
			nvidia,pins = "hdmi_cec_pcc0";
			nvidia,function = "cec";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
		};

		/* GPIO Pin Configuration */
		aud_mclk_pbb0 {
			nvidia,pins = "aud_mclk_pbb0";
			nvidia,function = "aud";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		spi2_mosi_pb4 {
			nvidia,pins = "spi2_mosi_pb4";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		spi2_miso_pb5 {
			nvidia,pins = "spi2_miso_pb5";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		spi2_sck_pb6 {
			nvidia,pins = "spi2_sck_pb6";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		spi2_cs0_pb7 {
			nvidia,pins = "spi2_cs0_pb7";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		spi2_cs1_pdd0 {
			nvidia,pins = "spi2_cs1_pdd0";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		pe6 {
			nvidia,pins = "pe6";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		cam_af_en_ps5 {
			nvidia,pins = "cam_af_en_ps5";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		cam1_pwdn_ps7 {
			nvidia,pins = "cam1_pwdn_ps7";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		cam2_pwdn_pt0 {
			nvidia,pins = "cam2_pwdn_pt0";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		sata_led_active_pa5 {
			nvidia,pins = "sata_led_active_pa5";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		pa6 {
			nvidia,pins = "pa6";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		als_prox_int_px3 {
			nvidia,pins = "als_prox_int_px3";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		temp_alert_px4 {
			nvidia,pins = "temp_alert_px4";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		button_power_on_px5 {
			nvidia,pins = "button_power_on_px5";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		button_vol_up_px6 {
			nvidia,pins = "button_vol_up_px6";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		button_home_py1 {
			nvidia,pins = "button_home_py1";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		lcd_te_py2 {
			nvidia,pins = "lcd_te_py2";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		lcd_bl_pwm_pv0 {
			nvidia,pins = "lcd_bl_pwm_pv0";
			nvidia,function = "rsvd3";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		lcd_bl_en_pv1 {
			nvidia,pins = "lcd_bl_en_pv1";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		pz0 {
			nvidia,pins = "pz0";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		pz2 {
			nvidia,pins = "pz2";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		pz3 {
			nvidia,pins = "pz3";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		dap4_fs_pj4 {
			nvidia,pins = "dap4_fs_pj4";
			nvidia,function = "i2s4b";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		dap4_din_pj5 {
			nvidia,pins = "dap4_din_pj5";
			nvidia,function = "i2s4b";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		dap4_dout_pj6 {
			nvidia,pins = "dap4_dout_pj6";
			nvidia,function = "i2s4b";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		dap4_sclk_pj7 {
			nvidia,pins = "dap4_sclk_pj7";
			nvidia,function = "i2s4b";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		uart2_rts_pg2 {
			nvidia,pins = "uart2_rts_pg2";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		uart2_cts_pg3 {
			nvidia,pins = "uart2_cts_pg3";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		spi1_mosi_pc0 {
			nvidia,pins = "spi1_mosi_pc0";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		spi1_miso_pc1 {
			nvidia,pins = "spi1_miso_pc1";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		spi1_sck_pc2 {
			nvidia,pins = "spi1_sck_pc2";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		spi1_cs0_pc3 {
			nvidia,pins = "spi1_cs0_pc3";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		spi1_cs1_pc4 {
			nvidia,pins = "spi1_cs1_pc4";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		wifi_en_ph0 {
			nvidia,pins = "wifi_en_ph0";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		wifi_wake_ap_ph2 {
			nvidia,pins = "wifi_wake_ap_ph2";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		ap_wake_bt_ph3 {
			nvidia,pins = "ap_wake_bt_ph3";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		bt_rst_ph4 {
			nvidia,pins = "bt_rst_ph4";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		bt_wake_ap_ph5 {
			nvidia,pins = "bt_wake_ap_ph5";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		ph6 {
			nvidia,pins = "ph6";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		ap_wake_nfc_ph7 {
			nvidia,pins = "ap_wake_nfc_ph7";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		nfc_en_pi0 {
			nvidia,pins = "nfc_en_pi0";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		nfc_int_pi1 {
			nvidia,pins = "nfc_int_pi1";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
		};

		gps_en_pi2 {
			nvidia,pins = "gps_en_pi2";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		usb_vbus_en0_pcc4 {
			nvidia,pins = "usb_vbus_en0_pcc4";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_UP>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
		};
	};

	pinmux_unused_lowpower: unused_lowpower {
		dvfs_clk_pbb2 {
			nvidia,pins = "dvfs_clk_pbb2";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		gpio_x1_aud_pbb3 {
			nvidia,pins = "gpio_x1_aud_pbb3";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		gpio_x3_aud_pbb4 {
			nvidia,pins = "gpio_x3_aud_pbb4";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		dap1_din_pb1 {
			nvidia,pins = "dap1_din_pb1";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		dap1_dout_pb2 {
			nvidia,pins = "dap1_dout_pb2";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		dap1_fs_pb0 {
			nvidia,pins = "dap1_fs_pb0";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		dap1_sclk_pb3 {
			nvidia,pins = "dap1_sclk_pb3";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		dmic3_clk_pe4 {
			nvidia,pins = "dmic3_clk_pe4";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		dmic3_dat_pe5 {
			nvidia,pins = "dmic3_dat_pe5";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		cam_rst_ps4 {
			nvidia,pins = "cam_rst_ps4";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		cam_flash_en_ps6 {
			nvidia,pins = "cam_flash_en_ps6";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		cam1_strobe_pt1 {
			nvidia,pins = "cam1_strobe_pt1";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		motion_int_px2 {
			nvidia,pins = "motion_int_px2";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		touch_rst_pv6 {
			nvidia,pins = "touch_rst_pv6";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		touch_clk_pv7 {
			nvidia,pins = "touch_clk_pv7";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		touch_int_px1 {
			nvidia,pins = "touch_int_px1";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		modem_wake_ap_px0 {
			nvidia,pins = "modem_wake_ap_px0";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		button_vol_down_px7 {
			nvidia,pins = "button_vol_down_px7";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		button_slide_sw_py0 {
			nvidia,pins = "button_slide_sw_py0";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		lcd_rst_pv2 {
			nvidia,pins = "lcd_rst_pv2";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		lcd_gpio1_pv3 {
			nvidia,pins = "lcd_gpio1_pv3";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		ap_ready_pv5 {
			nvidia,pins = "ap_ready_pv5";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		clk_32k_out_py5 {
			nvidia,pins = "clk_32k_out_py5";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pz4 {
			nvidia,pins = "pz4";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		clk_req {
			nvidia,pins = "clk_req";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		cpu_pwr_req {
			nvidia,pins = "cpu_pwr_req";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		uart1_rts_pu2 {
			nvidia,pins = "uart1_rts_pu2";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		uart1_cts_pu3 {
			nvidia,pins = "uart1_cts_pu3";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pk0 {
			nvidia,pins = "pk0";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pk1 {
			nvidia,pins = "pk1";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pk2 {
			nvidia,pins = "pk2";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pk3 {
			nvidia,pins = "pk3";
			nvidia,function = "rsvd2";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pk4 {
			nvidia,pins = "pk4";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pk5 {
			nvidia,pins = "pk5";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pk6 {
			nvidia,pins = "pk6";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pk7 {
			nvidia,pins = "pk7";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pl0 {
			nvidia,pins = "pl0";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pl1 {
			nvidia,pins = "pl1";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		spi4_mosi_pc7 {
			nvidia,pins = "spi4_mosi_pc7";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		spi4_miso_pd0 {
			nvidia,pins = "spi4_miso_pd0";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		spi4_sck_pc5 {
			nvidia,pins = "spi4_sck_pc5";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		spi4_cs0_pc6 {
			nvidia,pins = "spi4_cs0_pc6";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		wifi_rst_ph1 {
			nvidia,pins = "wifi_rst_ph1";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		gps_rst_pi3 {
			nvidia,pins = "gps_rst_pi3";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		pcc7 {
			nvidia,pins = "pcc7";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
		};

		spdif_out_pcc2 {
			nvidia,pins = "spdif_out_pcc2";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		spdif_in_pcc3 {
			nvidia,pins = "spdif_in_pcc3";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
		};

		usb_vbus_en1_pcc5 {
			nvidia,pins = "usb_vbus_en1_pcc5";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
		};
	};

	drive_default: drive {
	};
};

};

dmesg after flash nano

dmesg | grep DTS
[ 0.211762] DTS File Name: arch/arm64/boot/dts/…/…/…/…/…/…/hardware/nvidia/platform/t210/porg/kernel-dts/tegra210-p3448-0000-p3449-0000-a02.dts
[ 0.420051] DTS File Name: arch/arm64/boot/dts/…/…/…/…/…/…/hardware/nvidia/platform/t210/porg/kernel-dts/tegra210-p3448-0000-p3449-0000-a02.dts

TEGRA GPIO
sudo grep “Name:|J:|BB:” /sys/kernel/debug/tegra_gpio
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
J: 2:1 00 00 00 00 00 00 000000
BB: 6:3 00 00 00 00 00 00 000000

configuration amixer

amixer -c tegrasndt210ref sget “I2S4 Mux”
Simple mixer control ‘I2S4 Mux’

To complete the info about the configuration:

sudo grep dap4 /sys/kernel/debug/tegra_pinctrl_reg
Bank: 1 Reg: 0x70003144 Val: 0x00000044 → dap4_fs_pj4
Bank: 1 Reg: 0x70003148 Val: 0x00000044 → dap4_din_pj5
Bank: 1 Reg: 0x7000314c Val: 0x00000004 → dap4_dout_pj6
Bank: 1 Reg: 0x70003150 Val: 0x00000044 → dap4_sclk_pj7

My friends!! the configuration explained work after to adjust the mixer using:

amixer -c tegrasndt210ref cset name=‘I2S4 Mux’ MVC1
112 amixer -c tegrasndt210ref cset name=‘MVC1 Mux’ ADMAIF1
113 amixer -c tegrasndt210ref cset name=‘MVC1 Vol’ 12000
114 amixer -c tegrasndt210ref cget name=‘MVC1 Vol’
115 amixer -c tegrasndt210ref cset name=‘MVC2 Mux’ I2S4

Best Regards

The last problem that i have is: work only the left speaker. not the right. if someone can explain me how i can put volume in the right speaker?

Hello!

The MVC by default should apply the volume control to all channels (with a max of 8 channels supported). Make sure that the ‘MVC1 Channels’ is set to 0 (which means that it will not override the number of channels specified by the arecord command) …

$ amixer -c tegrasndt210ref sget 'MVC1 Channels'
Simple mixer control 'MVC1 Channels',0
  Capabilities: volume volume-joined
  Playback channels: Mono
  Capture channels: Mono
  Limits: 0 - 8
  Mono: 0 [0%]

Do you know what mic is on this audio card? What sample size are you using? I am not sure if it is the same Mic that is used on the Adafruit I2S MEMS Mic board (Adafruit I2S MEMS Microphone Breakout - SPH0645LM4H : ID 3421 : $6.95 : Adafruit Industries, Unique & fun DIY electronics and kits), however, I recall that this Mic outputs 24-bit samples and so we capture these using a 32-bit sample size.

Regards,
Jon

hi could you tell how to boot to u-boot command line ?

Hello!

The u-boot command line is accessible via the serial console. Please see the following …

Regards,
Jon

My goal is to interface with an external codec, via I2S4 on the 40-pin header, which is converting four analog audio signals into a single time domain multiplexed (TDM) I2S data stream.

I am able to see appropriate MCLK, BCLK, and LRCLK operation on an oscilloscope. At this time I am capturing a null audio stream because I have not connected my external audio board.

I would like to take the TDM I2S data and route it to four separate files for analysis (1 per channel).

Current State:

  • Edited pinmux and rebuilt/flashed u-boot with I2S4 configuration:
    (NOTE: DAP4_DOUT_PJ6 is intentionally not muxed as SFIO, it is used as GPIO for my application.)
PINCFG(DAP4_FS_PJ4,          I2S4B,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
PINCFG(DAP4_DIN_PJ5,         I2S4B,      NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
PINCFG(DAP4_DOUT_PJ6,        DEFAULT,    NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
PINCFG(DAP4_SCLK_PJ7,        I2S4B,      NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),

PINCFG(AUD_MCLK_PBB0,        AUD,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
  • Edited tegra210-porg-p3448-common.dtsi and generated/flashed updated DTB:
i2s_dai_link1: nvidia,dai-link-1 {
    linke-name = "spdif-dit-0";
    cpu-dai = <&tegra_i2s4>;
    codec-dai = <&spdif_dit0>;
    cpu-dai-name = "dit-hifi";
-   format = "i2s";
+   format = "dsp_a";
    bitclock-slave;
    frame-slave;
    bitclock-noninversion;
    frame-noninversion;
-   bit-format = "s16_le";
+   bit-format = "s24_le";
    bclk-ratio = <1>;
    srate = <48000>;
-   num-channel = <2>;
+   num-channel = <4>;
    ignore_suspend; 
    name-prefix = "x";
    status = "okay";
  }

Questions:

  • I’ve read about ADX, but have not found useful documentation. Is this the preferred method for routing TDM audio data to separate files?
  • I’ve also read about FFmpeg. The documentation is readily available. Is this an appropriate utility for routing the audio data?
  • Do I need to edit any other .dtsi files? (e.g. tegra210-audio.dtsi or tegra210-soc-base.dtsi)

Thank you in advance,
Kai