Hello!
Can you tell me how you detect that the slots are shifted? Are you looping the data back out again? If so please let me know how you are doing this.
Looking at the above, I don’t believe you need to set ‘I2S4 fsync width’ at all because the I2S is the slave. My understanding that this is used when the I2S is the master and configures how long the fsync width is. However, I doubt that this is the problem.
When you execute the ‘alsactl init tegrasndt210ref’ it is executing the script in ‘/usr/share/alsa/init/postinit/00-tegra.conf’. It would be interesting so see if there is one particular setting that causes it to realign. You could dump the settings before and after doing this to see the difference to help isolate what is actually changing …
$ alsactl store -f before.txt
$ alsactl init tegrasndt210ref
$ alsactl store -f after.txt
Then diff’ing the before.txt and after.txt will show you what changed and then you can try to determine which of these is making a difference.
Regards,
Jon