Is there the way to program Nano so that second i2s channel route to 40-pin header from m.2?

Hi everybody!
Is there the way to program Nano so that second i2s channel route to 40-pin header from m.2?
For example, with creating custom device tree overlay?
Thanks is advance.

Hello!

Are you asking if it is possible to expose two I2S interfaces on the 40-pin header? If so, then unfortunately that is not possible. There are two I2S interfaces available on the Nano DevKit; one on the M.2 connector and one on the 40-pin header. However, you can only access these via the respective headers.

Regards,
Jon

Yes, exactly what I mean to say. So can you advice me which codec can pack several i2s to TDM? I would highly appreciate if you can!

I will make a guess:dsp processor on the base of “adau 1452”?

Hello!

We typically don’t recommend any particular 3rd party codec’s, but if a codec support the DSP-A/B timing for TDM, then it should work with Jetson Nano. Jetson can support upto 16 channels per I2S interface.

I am not sure you need to have a DSP processor, just an audio codec that supports TDM and has the number of audio inputs/outputs you require. For example, I have seen people using an 8 channel ADC …

Regards,
Jon

yes 1452 supports tdm4, tdm8, tdm16 output, but how to make sure that it is a DSP-A/B timing conformant?

Hello!

The datasheet for the device should fine what modes/formats it supports. Otherwise, the vendor should be able to confirm.

Jon

Thank you a lot, Jon!

Hello!

Please note that integrating audio codecs is not trivial in Linux in general. So per the Jetson audio documentation we recommend …

When you choose an audio codec to use with a Jetson device, be sure that:

•It is hardware-compatible in terms of functional pins (I2S, DMIC, etc.), GPIO, power, and clocks required to support the codec.

•It is compatible with the Jetson I2S interface (sample rates, sample sizes, frame formats, etc.).

•A Linux kernel driver is available for the codec

•ALSA examples are available for it to show how to configure its audio routing and general setup. Configuring the audio routing can be the most complex part of integrating an I2S codec.

https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide%2Fasoc_driver.18.2.html%23wwpID0E0CU0HA

The last point is critical. I see a lot of people attempting to integrate codecs with Jetson and the configuration of the codec is where people really struggle. Given that each codec is different, there is no commonality to configuring codecs. Therefore, it is recommended that you understand how to integrate and configure the codec before selecting.

Regards,
Jon

I thought I must make codec to generate TDM with clock supported, correct device tree to say to nano that on i2s pin is TDM with fsync. Ok, I would read carefully manuals!

Thank you again!

Hello!

It is a lot more complex that just getting the interface configuration correct. For example, if you look at the following there were quite a few steps to integrate this codec …

Regards,
Jon

Thank you for warning. I will learn codec datasheet to clear all questions! May be will post questions occured to forum.

Hi Jon!
I can not find specification for ‘DSP-A/B timing for TDM’ in any datasheet. Can you tell me what exactly DSP-A/B timing means? Link maybe …
Thanks in advance.

Hello!

I found some good timing diagrams in the following doc …

Per the Tegra I2S driver, DSP-A implement a 1-bit delay and DSP-B implements a 0-bit delay from the start of the sync to the first data …

https://nv-tegra.nvidia.com/gitweb/?p=linux-nvidia.git;a=blob;f=sound/soc/tegra-alt/tegra210_i2s_alt.c;h=9d1bcf83e3b475659bac24394acb7179d10b4ef2;hb=230cb880e212aab814e5e0885f87c76b70e762c7#l292

Regards,
Jon

aha, I see …
another one question, please - and what frequency rate which comes from 12 pin to codec - 24.576 mhz?

Hello!

Pin 12 is the I2S bit clock and so the frequency is number-of-channels * bits-per-sample * sample-rate.

So for 16-bit stereo @ 48kHz it would be … 2 * 16 * 48000 = 1.536MHz.

Please note that there is also the AUD_MCLK (on pin 7) that operates, by default, as 256 * sample-rate. So for 48kHz, it would be 12.288MHz.

Regards,
Jon

yes, question was how to set rate which are suited for TDM8 : 8 channels, 16 khz sampling rate and 16 bits per sample? or nano i2s channel would have slave mode?

Hello!

The bit clock frequency is configured per the parameters passed to aplay/arecord or whatever userspace app is being used.

For example, if you were to …

$ aplay -D hw:tegrasndt210ref,0 -c 2 -r 48000 -f S16_LE

The bit clock would be configured to be 2 * 16 * 48000 = 1.536MHz.

Or if you are using 8 channels …

$ aplay -D hw:tegrasndt210ref,0 -c 8 -r 48000 -f S16_LE

The bit clock would be configured to be 8 * 16 * 48000 = 6.144MHz.

Jon

aha, and the same with arecord apparently …
arecord -D hw:tegrasndt210ref,0 -c 8 -r 16000 -f S16_LE - the command suited for TDM8 input
Thanks a lot!

Hi Jon!
I suppose following sets DSP-A mode?

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