Is there the way to program Nano so that second i2s channel route to 40-pin header from m.2?

Hi Jon!
Can you tell me which command line for setting fixed master clock rate for 12.288MHz, please. I mean ‘nvidia,mclk-rate’ property in DT.
Thank you in advance.

Hello!

I am not sure what this screen capture is taken from. However, it appears that that setting is only setting the MSB position. A 1-bit delay is correct for DSP-A, but I think that you may also need to configure the LRCLK Type and LRCLK Polarity as well. However, I am not sure as I am not familiar with this tool.

Regards
Jon

Hello!

In the latest L4T release, the ‘nvidia,mclk-rate’ has been removed in favour of using the standard Linux kernel ‘assigned-clocks’ properties for configuring clocks. Please see section “AUD_MCLK for Codec SYSCLK” in …

https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide%2Fasoc_driver.18.2.html%23wwpID0E0RS0HA

Regards,
Jon

Hi Jon!
Thank you for reply!
I found out already that mclk-rate in not a valid term anymore, and I got required master rate (12,288MHz) with mclk-fs scaling factor.
But assigned-clock-rates which must set fixed mclk rate is not working for me.
It is not much important now, though.
Vladimir

Hi Vladimir,

Thanks for the response. If you do revisit this and need further assistance, please let us know.

Regards,
Jon

Thank you a lot Jon! Maybe in the future, but now mics array is working and I concentrate on soft that would be working inside Nano. Vladimir