How to enable audio master clock on the 40 pin header?

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
1

I would like to generate a constant 24.576 Mhz audio master clock output from the Orin AGX 40 pin header. I have set up the pin configuration using the opt/nvidia/jetson-io/jetson-io.py tool, but pin 7 (aud_mclk) is listed as unused, despite enabling I2S / TDM capability.

As a sanity check, I am able to send / receive TDM data on the rest of the signals on the 40 pin header (FS, BCLK, DOUT, DIN, looked at using an oscilloscope and logic analyzer, so I can confirm that the I2S/TDM peripheral is working). The audio master clock signal is not present (the signal is constant high).

Thanks for any assistance.

3

Have you checked Audio Setup and Development — Jetson Linux Developer Guide documentation (nvidia.com)?

4

I have, but its not totally clear to me how to set up this clock. I assume for someone with more experience than I in properly updating the nodes in the device tree, its trivial, but I’m a tad overwhelmed with all the things I need to know to piece it together right now.

I see there is an extperiph4_clk in the jetson-io.py tool that I can also enable. However, its not clear to me how to configure that clock.

5

Ok, here is something basic, the extperiph4_clk does not list plla_out0 as a possible parent.

root@orin-a536ca:/sys/kernel/debug/bpmp/debug/clk/extperiph4# cat possible_parents 
pllp_out0 clk_32k clk_m 
root@orin-a536ca:/sys/kernel/debug/bpmp/debug/clk/extperiph4#

The I2S2 block is sourced from plla_out0 but it looks like it can also be sourced from the pllp_out0 block.

root@orin-a536ca:/sys/kernel/debug/bpmp/debug/clk/i2s2# cat possible_parents 
plla_out0 plla1_out1 i2s2_sync_clk pllp_out0 clk_m 
root@orin-a536ca:/sys/kernel/debug/bpmp/debug/clk/i2s2# cat parent 
plla_out0
root@orin-a536ca:/sys/kernel/debug/bpmp/debug/clk/i2s2#

What is required to switch the I2S2 block to be sourced (properly) from the pllp_out0 so that the master clock and the I2S2 block can both be synchronized?

7

Hi chriskeeser

There is no support to use pllp_out0 for audio IO operations. Alternatively you can try following options:

  1. Not sure the audio codec or board you are using over 40-pin header. But is it possible that codec can derive the MCLK from external source? Typically few codecs can generate the system clock from onboard oscillator. Please check if this applies to your case.

  2. Can your audio codec generate system clock based on the incoming I2S bit clock? If yes this can be used. In this case, Tegra I2S will be producer and the codec will be in consumer mode.

  3. If above options don’t work, then you can try first by using PLLP_OUT0 for MCLK and see if you see clock sync problems.

  4. If none of the options work, then you can hack a bit to update clock parent for I2S and MCLK in device tree. However you need to make sure if there is some other client which requests a different rate for PLLP. In that case you may not get a desired result at runtime.

8

@spujar Thank you for the information. I would be perfectly happy to do # 2, however, the bitclock stops whenever playback or recording completes. Is there is method to enable the bitclock and keep it running even when playback or recording stops?

The answers to your questions are below:

  1. We are using multiple ADAU1787 Codecs, and yes, they can derive their own master clock / sysclk from a crystal connected to them. However, this would require a change to the hardware and I would prefer to explore options that do not require board re-spins if its possible.
  2. Yes, the Codec supports getting a sysclk from the bit clock (and we actually use that currently with other hardware). The main need is for the bitclock to stay active after playback / recording stops so that the PLL can stay syncrhonized. We dont change the I2S/TDM format and keep everything constant from startup to shutdown. So, if there is a way to start the bitclock and keep it running, that would be perfectly acceptable too!
  3. Currently the PLLP_OUT0 is set to a 24.000 Mhz clock and we need a 24.576 Mhz clock. Its not (yet) clear to me how to configure the PLLP_OUT0 for this frequency, but as you probably guess, that might break other peripherals that rely on the 24 Mhz PLLP setting
  4. I would love to know how to modify the clock parent for the I2S system (however, I am missing some information on what to do and where in the device tree), and understand that there may be multiple consumers of the PLLP that might have different clocking needs that are in conflict.

Was I mistaken (or is the documentation in error) that pin 7 of the 40 pin GPIO header is intended to be the I2S master clock?

Thank you for answering my questions and making suggestions! The help is greatly appreciated.

9

Check if you can follow this to enable i2s bit block via debugfs.
https://docs.nvidia.com/jetson/archives/r35.4.1/DeveloperGuide/text/SD/Clocks.html?highlight=enable%20clock#overriding-default-clock-rates

The boards which have onboard codec the MCLK is routed there. In this case, on AGX Orin, the MCLK clock is routed to onboard RT5640 audio codec. So 40-pin does not have a dedicated MCLK here.