Setting AUDIO_MCLK to output


I am trying to capture via I2S on the X1 on my custom hardware. Currently I have an external ADC which is suppossed to send I2S data to the I2S0 port of the X1 SOM.

Unfortunately I am using my externel ADC in a master mode with the X1 as a Slave and I am using the AUDIO_MCLK source as my system clock source for my ADC.

Checking the AUDIO_MCLK pin on a scope shows now output though.

To clarify I am using pin F1. I also checked this pin on the Jetson X1 eval board where it is routed to the J21 expansion header ( and it too shows no output.

I also tried enabling via /sys/kernel/debug/clock/ by setting the states to ‘1’ but still getting no output.

I have the following pinmux settings for the clk in the file


pinmux_default: common {
			/* SFIO Pin Configuration */
			aud_mclk_pbb0 {
				nvidia,pins = "aud_mclk_pbb0";
				nvidia,function = "aud";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;

I have tried various other combinations.

Being that this aud_mclk is muxed with gpio 216, i tested setting it to GPIO and was able to see the switch on the J21 header so I know it is being set properly.

Any ideas why this clock would be generating?

From HW perspective, the connection of AUD_MCLK is OK.

I’m not familiar with SW configuration, but maybe you can check section 12.6.107 APBDEV_PMC_CLK_OUT_CNTRL_0 of TX1 TRM doc, seems the dap_mclk1_out is the corresponding control bits. Hope this can help you.

Yeah I believe the HW is all hooked up fine.

Again i’ve checked on my hardware as well as the jetson board and both show the same symptom where the audio_mclk0 is not producing any signal. I’ve tried probing it will also running aplay and arecord to see if that was the issue but still no clock is generated

I’m just trying to make that clock produce the standard 24MHz i need.

Does anyone know how in software to get this pin ‘F1’ AUDIO_MCLK to produce this output.

For audio MCLK, please check the following

  1. pin mux setting.
  2. whether that pin is requested by GPIO?
  3. As I know, Jetson TX1 does not mount audio codec. You may check the driver sound/soc/tegra/tegra_rt5639.c and go through mclk-related function. A codec driver should be up first.


Hey Jachen

  1. i put my pinmux setting up above. i believe i only have to set it in the dts file like shown. can you verify?

  2. I don’t believe that it is being exported as a GPIO. is there any way to verify this? I previously did export it as a test just to see if i had it as a correct pin and upon exporting (using /sys/class/gpio) i was able to toggle it and see it on the scope.

  3. I am currently mounting the audio codec tegra_t210ref_mobile_rt565x_alt.c found in sound/soc/tegra-alt/ and am force mounting it as a dummy codec (since i am using an external codec).
    I also manually made sure all the clocks requested in that driver get set. Unfortunately i dont konw if any of these clocks apply to AUD_MCLK though. Seems they refer to mclk as ‘pll_a’.

Hello, x1tester62:

  1. For DTS part, please change tristate to TEGRA_PIN_DISABLE
  2. tegra_asoc_utils_set_rate must be called to set mclk. Please track that function in the file you mentioned.
  3. when system is up, you can check the clock state by sfsfs node:


Hey Jachen,

  1. I previously had it as DISABLE and switched it to test some. It is back to ENABLE.

  2. What is the difference between the tegra-alt and regular tegra folders in the sound driver’s folder. I see both contain a variation of an rt5639 driver but the tegra-alt is what is used by default.

  3. What clock in the clock tree actually is the AUD_MCLK line? There isn’t a clock that is the exact name and there are many. Again i previously set all the clocks in the the clock tree to state on but still did not get a clock. Here are some i believe would be relevant.

pll_a                                 on     1   x9.5..   368639844
            pll_a_out0                         on     3   10.0     36863985
               extern1                         on     3   3.0      12287995
                  clk_out_1                    on     2   1.0      12287995
               d_audio                       $ on     2   1.0      36863985
                  vdd_core                                        800 mV
                  d_audio_slcg_ovr           $ off    0            36863985
               dmic3                           off    0   11.0     3351272
               dmic2                           off    0   11.0     3351272
               dmic1                           off    0   11.0     3351272
               spdif_out                     $ off    0   21.0     1755428
                  vdd_core                                        0 mV
               i2s4                            off    0   5.50     6702543
               i2s3                            off    0   5.50     6702543
               i2s1                            off    0   5.50     6702543
               i2s0                            on     1   24.0     1536000
              *pll_a_out0_out_adsp             off    0   1.0      36863985
           *pll_a_out_adsp                     off    0   1.0      368639844

   i2s4_sync                                   on     1            24000000
   i2s3_sync                                   on     1            24000000
     *audio3                                   off    0            24000000
   i2s2_sync                                   on     1            24000000
   i2s1_sync                                   on     1            24000000
     *audio1                                   off    0            24000000
   i2s0_sync                                   on     1            24000000
   spdif_in_sync                               on     1            24000000
     *audio2_dmic                              off    0            24000000
     *audio1_dmic                              off    0            24000000
     *audio0_dmic                              off    0            24000000
     *audio                                    off    0            24000000
        *audio_2x                              off    0   x2       48000000
     *audio4                                   off    0            24000000
     *audio2                                   off    0            24000000
     *audio0                                   off    0            24000000

Seems like even though I set the pinmux correctly, the GPIO216 was still somehow causing an issue.

I was able to get my clock generated by exporting 216 and then unexporting it and then suddenly my clock came through.

I am still very confused why this is the case since I pinmux-ed everything correctly and 216 wasn’t exported by default. Any ideas?

Now im moving on to actually getting my external codec to work and capture I2S.

Hello, x1tester62:
You mean you can get mclk by export and unexport gpio 216?

What’s the version of SDK you are using?


I am still on 23.2.

And yes even though i set all the pinmux values correctly (to my knowledge) in the pinmux dts, the gpio driver at some level must still be stealing that pin.

I had the same situation for the other I2S pins I used as well (I2S1_SDATA_IN, I2S1_LRCK, I2S1_SCLK). For each of these i had to run export then unexport on their GPIO pins to get them to work.

So doing the following:

echo 216 > /sys/class/gpio/export #AUD_MCLK
echo 8 > /sys/class/gpio/export #LR 
echo 9 > /sys/class/gpio/export #Data in
echo 11 > /sys/class/gpio/export #BCLK
echo 8 > /sys/class/gpio/unexport
echo 9 > /sys/class/gpio/unexport
echo 11 > /sys/class/gpio/unexport
echo 216 > /sys/class/gpio/unexport

Using a scope probe, i could visually see the only time these pins worked in their I2S state was when i exported and then unexported.

For example for pin 216, after exporting and unexporting the signal suddenly starts coming through as a clean 12.288MHz clock as needed.

So i now have audio coming in successfully any everything.


Hello, x1tester62:
That’s weird. Would you please do GPIO export/unexport as a WAR and keep your development going. I will try to check this issue in my platform. It may take some time.

thanks for pointing out that.


Hey Jachen,

Yes that is my plan for now. I already have it built into my startup scripts.

Just let me know if you find anything or if it is just on my end. Am curious if I am still making some other mistake. Thanks!

Hello friends,

Happy owner of a TX1 for my kobuki,

trying to export sound via I2S to an adafruit audio amplifier (to 3w speakers)

Could you please help me to find J21 audio output pins…

The small board needs :

[i]- Left/Right clock

  • Bit clock
  • Data IN[/i]

Should it be :

PIN 35 : AUDIO I2S #0 Left/Right Clock
PIN ???

Where is Bit clock ??

Am I right ? Big thanks friends.


I see pin 7 shown on one schematic as “AUDIO_I2S_MCLK_3V3”…this is probably what you want.

thanks for your quick answer.
Well, not sure !!

adafruit board says doesn’t need MCLK connection (leave it disconnected)

board needs BCLK (tells the amplifier when to read data on the data pin)

Is there a BCLK outpin ?

I think having an actual bit clock is better, but you could rig something based on data level changes (any differential signal, such as this, has lower jitter with a real clock…if having one less wire is more important you can estimate a clock based on data…it depends on how you feel about jitter). The other clock would also be known as the word clock or left-right clock, but this may be referred to in some of the docs as the audio sync clock…I can’t guarantee it but pin 12 (abbreviated AUDIO_I2S_SRCLK_3V3) is probably the clock for selecting left-right. Maybe someone could verify this.

yes, that sounds good !
I’ll try this and will post here results.
Thanks linuxdev

I am trying to import sound via I2S to an adafruit microphone(3421).
Can anybody help by confirming the pins(audio_mclk and sclk) and help with further steps.
Any help would be highly appreciated.