I2S MCLK on Jetson TX2

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

Hello,

Currently during aplay command the AUDIO_MCLK clock via pin 7 on the J21 connector is measured to be 9MHz where should this value be modified to 12MHz?

Regards,

Igal

2

Isn’t there anyone in NVidia support that can reply on how to configure I2S clock out?

3

Hi Igal,

You should be able to do this by calling tegra_alt_asoc_utils_set_parent() as discussed here …

Also note my other comment below to comment out a call to clk_set_rate in tegra_alt_asoc_utils_set_rate() …

Hope this helps.

Regards
Jon

4

Jon, hi,

thanks for the prompt response (the links looks familiar :) )

and if all was set per the configuration and clock is 9[MHz]?

Regards,

Igal

5

Hi Igal,

Are you saying it is still 9MHz? You can always check what the kernel thinks by reading …

$ sudo grep -r aud_mclk /sys/kernel/debug/clk/clk_summary

Regards,
Jon

6

Jon, hi,

The clock there is 9,031,679[Hz].

Igal

7

Hi Igal,

Can you show me the complete output from …

$ sudo grep -r aud_mclk /sys/kernel/debug/clk/clk_summary

Regards,
Jon

8

Hi Igal,

Actually, please attach the complete output from …

$ sudo cat /sys/kernel/debug/clk/clk_summary

Regards
Jon

9

Jon, hi,

the full output is attached.

Igal

clk_summary.txt (33.2 KB)

10

Hi Igal,

The problem is that the parent clock for the aud_mclk is still the pll_a clock …

pll_a_vco                                               0            0   258000000   258000000          0 0  
    *[        default_freq                                       0]
       pll_a                                                0            0   270950390   270950400          0 0  
       *[        default_freq                                       0]
          pll_a_out0                                        0            0    45158398    45158400          0 0  
          *[        default_freq                                       0]
             aud_mclk                                       0            0     9031679     9600000          0 0  
             *[        default_freq                                       0]

The rate being requested is 9.6MHz and you are getting around 9.03MHz. In your tegra_t186ref_driver_probe() I see you were calling tegra_alt_asoc_utils_set_parent(). Is this still the case? If so, can you ensure that any calls to tegra_alt_asoc_utils_set_extern_parent() in tegra_t186ref_mobile_rt565x.c are commented out?

Regards,
Jon

11

Jon, hi,

Thanks for the instruction now the clock is 9.6[MHz]. I recall that this clock was supposed to be 12000000.

What might cause the gap?

Regards,

Igal

12

Hi Igal,

I am guessing any calls to tegra_alt_asoc_utils_set_extern_parent(). Did you check to see if this is being called?

Also did you comment out a call to clk_set_rate in tegra_alt_asoc_utils_set_rate()?

Regards,
Jon

13

Jon, hi,

Yes The function tegra_alt_asoc_utils_set_extern_parent() is being called and I have commented all invocations to this function in the file ( I hope I understood correctly the word “any”).

The function tegra_alt_asoc_utils_set_parent() is invoked.

Per out another discussion I have commented in the file tegra_asoc_utils_alt.c in the function tegra_alt_asoc_utils_set_rate() only in a single place the clk_set_rate() function.
The file is attached.
Should I comment out all other places too?
Regards,

Igal

tegra_asoc_utils_alt.c (14.7 KB)

14

Hi Igal,

Yes that sounds correct. What do you see now?

Regards,
Jon

15

Jon, hi,

I see now 9.6MHz and not 12[MHz].

Regards,

Igal.

16

Jon, hi,

another thing that I see now that just before entering the login screen the Bit clock provides (on connector J21 pin 12) is 19.2[MHz]. but when I run the speaker-test -Dhw:1,0 there is no Bit clock. The master clock does not change and is 9.6[MHz] in both occasions.

Regards,
Igal

17

Hi Igal,

Does /sys/kernel/debug/clk/clk_summary still show that the ‘aud_mclk’ is under the pll_a?

I will need to test but I will not be able to do so until next week.

Regards,
Jon

18

Hi Igal,

In the meantime you can add some prints around the clk_set_parent() calls in tegra_asoc_utils_alt.c to see who is setting the parent.

Regards,
Jon

19

Jon, hi,

I can see now that the requested clock is 12[MHz] while the actual clock is 9.6[MHz]. The parent clock of the aud_mclk is clk_m. I guess that the problem is deriving from 19,200,000 down to 12,000,00 one can divide either by 1 or by 2 (9,600,000[Hz]).
Shouldn’t it be 192[MHz] and not 19.2[MHz]?

The function clk_set_parent is invoked only once by the function in file tegra_t186ref_mobile_rt565x.c

Regards,
Igal

20

Hi Igal,

19.2MHz is correct and so we cannot use that clock as the parent afterall. We should be able to use the pll_p which is running at 408MHz. So can you try …

int tegra_alt_asoc_utils_set_parent(struct tegra_asoc_audio_clock_info *data,
			int is_i2s_master)
{
	int ret = -ENODEV;

	if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
		return ret;

	if (is_i2s_master) {
		ret = clk_set_parent(data->clk_cdev1, data->clk_pll_a_out0);
		if (ret) {
			dev_err(data->dev, "Can't set clk cdev1/extern1 parent");
			return ret;
		}
	} else {
		ret = clk_set_parent(data->clk_cdev1, <b>data->clk_pll_p_out1</b>);
		if (ret) {
			dev_err(data->dev, "Can't set clk cdev1/extern1 parent");
			return ret;
		}

		ret = clk_set_rate(data->clk_cdev1, 12000000); // was 13000000 i.k.
		if (ret) {
			dev_err(data->dev, "Can't set clk rate");
			return ret;
		}
	}

	return 0;
}
EXPORT_SYMBOL_GPL(tegra_alt_asoc_utils_set_parent);

Regards,
Jon