R32.3.1 tx2-4g: Please provide all registers and their values to make the audio work

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
,
1

Looks like my audio driver is built, and working, It look like my device tree is correct, aplay -Dplughw:1,0 ./cheering.wav give syslog messages of
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.175803] [AK4637] ak4637_set_bias_level(1572)
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.176304] [ak4637] ak4637_i2c_write: (addr,data)=(0, 40)
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.176666] [AK4637] ak4637_set_bias_level(1572)
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.177138] [ak4637] ak4637_i2c_write: (addr,data)=(0, 40)
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.178492] [AK4637] ak4637_hw_params(1394)
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.179005] [AK4637] ak4637_set_dai_mute mute[OFF]
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.179494] [ak4637] ak4637_i2c_write: (addr,data)=(7, 2)
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.179860] [AK4637] ak4637_set_dai_mute(1614) ret 1
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.179905] ak4637 8-0012: ASoC: Failed to unmute: 1
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.185465] [ak4637] ak4637_i2c_write: (addr,data)=(1, 4)
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.186563] [ak4637] ak4637_i2c_write: (addr,data)=(0, 44)
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.186941] [AK4637] ak4637_spklo_event(1205)
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.187936] [ak4637] ak4637_i2c_write: (addr,data)=(1, 6)
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.188305] [AK4637] ak4637_spklo_event(1205)
Sep 29 14:17:14 BaseSystem_0_10 kernel: [13544.188784] [AK4637] ak4637_spklo_event wait=1msec

but no sound. Ignore the two fails, looks like soc-io.c is incorrectly check return codes, 1 means good i2c .

Can you use devmem2 and show me all the registers and their values to make audio work. Figuring out the registers to look at is difficult, figuring out from the pinmux what the values are is even more difficult.

I think I have found aud_mclk_ and it is

sudo devmem2 0x02431020
/dev/mem opened.
Memory mapped at address 0x7f9af0e000.
Value at address 0x2431020 (0x7f9af0e020): 0x59

Is 0x59 correct?

Which register holds the actual value of the clock speed?

Thanks
Terry

5

any information? Really need the complete register set to make audio work on my tx2. R32.3.1.

Thanks,
Terry

6

Hi Terry,

May I know the use case you are trying to run?

Please refer to the Codec porting guide on how to interface a codec and see if anything is missing.

It will also be good to check troubleshooting section to see if you are hitting any of the issues listed.

Unless we know what exactly is the problem, the register dumps won’t help much.

If you want to see the clock rates of I2S interface or MCLK, please provide clock tree dump.
cat /sys/kernel/debug/clk/clk_summary

Thanks,
Sameer.

7

looked at your links, and got to this area in trouble shooting:

The I2C port connected to the codec is not configured with the proper pinmux settings. Check whether the default pinmux settings are correct for the desired I2C port in the platform-specific pinmux worksheet, which you can download by searching the Jetson Download Center for “pinmux.”
If the pinmux settings for the I2C port are not correct, set them as instructed in the “Pinmux Changes” section of the topic Jetson Module Adaptation and Bring-Up that applies to your platform.

What are the correct pinmux setting for the audio? What registers do I look at and what values are required.

What register makes the pin audio, instead of GPIO?

Do you have a dump of the correct registers for the tx2-4g?

I have a ak4637 part on our custom board, and it is built into the kernel, I have done the device tree changes based on multiple forum topics, and it seems to be close.

I showed that if I do a aplay I get ak4637 messages that look like it is getting the device ready, unmuting it and then mutes it and does some more device changes, so I think it is really close, based on the ak4637 messages

Is the released code for r32.3.1 setup for gpio or an audio device?

Where in Nvidia’s documentation is the COOKBOOK for setting up the pinmux/registers. In some forum topics you ask for pinmux info but NEVER say if the user’s pinmux is correct or not, some of the forum topics went back to 2017.

So back to my original question, what pinmux registers are needed and what are there values,

so I think you are looking for aud_mclk from the cat…

This is what is on my system:

pll_a_vco 0 0 258000000 258000000 0 0
*[ default_freq 0]
pll_a 0 0 270950390 270950400 0 0
*[ default_freq 0]
pll_a_out0 0 0 22579199 22579200 0 0
*[ default_freq 0]
aud_mclk 0 0 2822399 2822400 0 0
*[ default_freq 0]
dspk2 0 0 11289599 12288000 0 0
*[ default_freq 0]
dspk1 0 0 11289599 12288000 0 0

Also in the trouble shooting the section:
Sound Not Audible or Not Recorded

none of your scripts work for me, and do not show any data.

Thanks,
Terry

9

Hi Terry,

Since I2C is already working for your codec, I don’t think you should worry about the pinmux settings of it. However refer to Jetson-IO tool section to configure pinmux for I2S/MCLK. If this does not work, I will provide the pinmux reference values that are needed which are not readily available at my finger tips at the moment. The MCLK pinmux value you mentioned appears to be wrong though.

To see the default state of the pins refer to 40-pin guide for TX2

Can you check with latest code (32.6.1) and see if the steps defined in BSP references work for you?

Please dump the clocks after you start playback. It gives a correct reading of what is happening w.r.t clocks. Dump I2S clocks too. You can probe the clock signals to confirm if the rate matches with the dump.

As far as register dumps are concerned, there are multiple modules in the path and I don’t think it would be best to start analyzing register dumps to begin with. We may eventually get there, but lets first see if clocks/pinmux are fine.

Thanks,
Sameer.

10

  1. Jetson-IO tool did not work on my tx2, flashed and quit.

  2. please provide the registers.

  3. 40-pin guide for tx2 says that the default is gpio, so what pins do I change?

  4. I am running r32.3.1, please provide a link to the r32.6.1 BSP. Found r32.5.1 BSP, it is a huge tar file, what do you want me to look at?

  5. how do I dump the clocks, and dump i2s clock. I really know nothing about the physical nvidia hardware, I am a software guy, and understand linux, linux drivers, and can kind of find my way around the device tree. If I knew or could find the names of the audio pins I could look at the *.cfg files but again I have no clue how to setup for audio, I might be able to dump the registers

  6. I only ask Nvidia about things I can’t find documentation on. No where have I found any doc on this is how you set the pinmux to get the audio to work.

Thanks, and I appreciate a US person on the forum.

Normally there is no one to talk to except for overnight responses, another thing that drives me crazy, if the topic is going to string on for thirty post and it takes overnight for Nvidia to respond, skipping weekends, it take way too long to get simple questions answered.

Please feel free to forward my last statement to nvidia forum management, this customer finds support very SLOW.

Terry

11

Any more info available yet,

What is the power up default for 0x0c2f1c00 and 0x0c2f1c30

This is what is set up in my system

Value at address 0x2215000 (0x7fad535000): 0x0
Value at address 0x2431040 (0x7fa6d0c040): 0x440
Value at address 0x2215020 (0x7fb1e6d020): 0x0
Value at address 0x2431038 (0x7f9910e038): 0x400
Value at address 0x2215040 (0x7f8014f040): 0x0
Value at address 0x2431030 (0x7f9fe68030): 0x448
Value at address 0x2215060 (0x7fafe27060): 0x0
Value at address 0x2431028 (0x7f95f1c028): 0x440
Value at address 0x2215080 (0x7f84b58080): 0x0
Value at address 0x2431020 (0x7f7cd36020): 0x400
Value at address 0xC303028 (0x7f8bcd3028): 0x455
Value at address 0xC303030 (0x7fa31fc030): 0x405
Value at address 0x2431040 (0x7fb63e6040): 0x440
Value at address 0x2431038 (0x7fa68be038): 0x400
Value at address 0x2431030 (0x7f7d423030): 0x448
Value at address 0x2431028 (0x7fab11a028): 0x440
Value at address 0x2431020 (0x7f9ccfa020): 0x400
Value at address 0x2431040 (0x7f90fc8040): 0x440
Value at address 0x2431038 (0x7f94635038): 0x400
Value at address 0x2431030 (0x7faeb91030): 0x448
Value at address 0x2431028 (0x7f84999028): 0x440
Value at address 0x2431020 (0x7f7e72e020): 0x400
Value at address 0xC303028 (0x7f9fd2e028): 0x455
Value at address 0xC303030 (0x7fb1bf7030): 0x405
Value at address 0xC303028 (0x7f85d4e028): 0x455
Value at address 0xC303030 (0x7f79581030): 0x405

How does this look?

Terry

12

So used the template and found that TEGRA_GPIO(J, 0)
was removed from the dtsi file. What line needs to be removed from the *.cfg file to remove TEGRA_GPIO(J, 0)

We know that the template and what I am using to build r32.3.1 do not match, so I have to add remove things from the cfg file by hand

Nvidia messed up because they need to release a template for each release of the system r32.3.1 needs a template, and I assume that r28.x.x needed a different template

Thanks,
Terry

13

@kayccc Why no response to my input? I have to get this part working and really need NVIDIA’s help.

It started out good, and then went silent. Whats up? I need information Please.

Thanks,

Terry

14

Please be patient, our team are located in different timezone, we will give the update soon.

15

Hi Terry,

Thanks for your patience. Please follow below steps.

  • I would strongly suggest you to check 32.6.1 release:
    You can upgrade to latest release by using NVIDIA SDK Manager reference.

  • The Jetson-IO tool is expected to work with 32.6.1 release. Configure ‘aud_mclk’ and ‘i2s1’ pins as per the suggested steps in the document.

    Once you configure, you should see following settings.

    Bank: 0 Reg: 0x02431020 Val: 0x00000400 -> aud_mclk_pj4
Bank: 0 Reg: 0x02431028 Val: 0x00000444 -> dap1_fs_pj3
Bank: 0 Reg: 0x02431030 Val: 0x00000454 -> dap1_din_pj2
Bank: 0 Reg: 0x02431038 Val: 0x00000404 -> dap1_dout_pj1
Bank: 0 Reg: 0x02431040 Val: 0x00000444 -> dap1_sclk_pj0

  • Once above setting is done, run your audio use case. As I mentioned earlier please check codec porting guide and troubleshooting techniques if things don’t work as expected. Provide logs as per sound not audible or recorded section in the doc. If some step does not work, please mention what you tried and what did not work. Also please attach the DT or driver code you added or modified.

  • To check clocks dump following information:
    cat /sys/kernel/debug/clk/clk_summary
    You can specifically grep for i2s1 and aud_mclk clock along with their parents. Please dump this info after you start your use case. You can probe the clock signals to actually verify them.

  • Simply providing the registers won’t help. We need to see what is working and what is not. Rule out the options which already work and then focus on something which is known to be problematic. As I see with your inputs so far, I2C seems to be working and your codec is responding. Please check above steps and provide the requested logs.

Thanks,
Sameer.

16

  1. Too much time an money spent on r32.3.1 to change at this time.

  2. changed to your values for the registers and nothing changed.

  3. clk summary stuff does this look correct?
    sudo cat /sys/kernel/debug/clk/clk_summary | fgrep mclk
    aud_mclk 0 0 3175097 2822400 0 0
    tbuckley@BaseSystem_0_10:~/tmp/exploringBB/chp14/audio$ sudo cat /sys/kernel/debug/clk/clk_summary | fgrep i2s1
    i2s1_sync_input 0 0 176400 176400 0 0
    i2s1_sync_clk 0 0 0 0 0 0
    i2s1 0 0 176399 176400 0 0

  4. will work on sound not audible or recorded log.

  5. cat /sys/kernel/debug/asoc/codecs shows ak4637.8-0012 is this correct and good?

  6. /sys/kernel/debug/tracing/event shows enable: empty

  7. also looks like all the files in /sys/kernel/debug/tracing are empty.

  8. What does this mean and how do I do it?
    You must ensure that the physical codec pins (input/output, IN1P, and IN2P in this case) are connected directly or indirectly to codec DAI’s AIF_OUT/AIF_IN. AIF_OUT/AIF_IN (AIF1 Capture in this case) interface with the CPU DAI (I2S in this case), which in turn must be connected directly or indirectly to the platform DAI (ADMAIF in this case).

9.will attach dmesg, dtc, and settings.txt as per your documentation
setting.txt (299.4 KB)
dtc (254.2 KB)
dmesg (81.8 KB)
log.txt (25.6 KB)

  1. from the doc, what do you need for my system r32.3.1.tx2-4g for registers
    Register dump of I2S being used while running the use case, for example:
    $ cat /sys/kernel/debug/regmap/tegra210-i2s.3/registers > ~/i2s4__reg_dump
    (This command is for I2S3 on a T210-based device. Change the pathname as appropriate for your carrier board and I2S channel.)
17

Hi Terry,

It does not look correct. I don’t see the clock state to be enabled (you can map the values with top row, which has labels to what each column in the dump mean). Did you dump this clock after you started aplay?

For ex:

aplay -Dplughw:1,0 ./cheering.wav &
sleep 1
cat /sys/kernel/debug/clk/clk_summary

Can you also attach “cheering.wav” file or provide ‘mediainfo’ dump of the file?
Depending on its sample rate, channels and bits per sample I2S clock or MCLK clock is set. Unless I know the details of this file, I cannot comment on the clock rates.

For ex:

spujar@audio:~/Public$ mediainfo 10.wav
General
Complete name                            : 10.wav
Format                                   : Wave
File size                                : 5.12 MiB
Duration                                 : 30s 450ms
Overall bit rate mode                    : Constant
Overall bit rate                         : 1 411 Kbps

Audio
Format                                   : PCM
Format settings, Endianness              : Little
Format settings, Sign                    : Signed
Codec ID                                 : 1
Duration                                 : 30s 450ms
Bit rate mode                            : Constant
Bit rate                                 : 1 411.2 Kbps
Channel(s)                               : 2 channels
Sampling rate                            : 44.1 KHz
Bit depth                                : 16 bits
Stream size                              : 5.12 MiB (100%)

This appears good. It means your codec driver is registered fine.

I am not sure why you are not able to see this. But lets come to this later. We need to first see if the clocks rates are as expected and they should get enabled as soon as you start aplay.

Use “cat /sys/kernel/debug/regmap/tegra210-i2s.0/registers > ~/i2s1__reg_dump”

The sound card is registered fine with your codec. You can see all the codec mixer controls to be available. There are many controls, I am just listing few for reference. You can check the ones with prefix ‘x …’.

numid=1152,iface=MIXER,name='x SPKLO Mixer BEEPS'
  ; type=BOOLEAN,access=rw------,values=1
  : values=on
numid=1151,iface=MIXER,name='x SPKLO Mixer DACL'
  ; type=BOOLEAN,access=rw------,values=1
  : values=on
numid=1150,iface=MIXER,name='x SPKLO Mixer DACS'
  ; type=BOOLEAN,access=rw------,values=1
  : values=on
numid=865,iface=MIXER,name='x Speaker Output Volume'
  ; type=INTEGER,access=rw---R--,values=1,min=0,max=3,step=0
  : values=0
  | dBminmax-min=6.40dB,max=14.90dB
numid=906,iface=MIXER,name='x Thermal Shutdown Auto Power Up'
  ; type=BOOLEAN,access=rw------,values=1
  : values=on

It does not have any error log. I hope this you have captured after aplay finishes.

Generally codec driver defines input and output pins using SND_SOC_DAPM_INPUT() and SND_SOC_DAPM_OUTPUT() respectively. These must be connected to machine source and sink widgets to complete the DAPM routing paths. Can you please attach the codec driver and the related datasheet?

I see you have changed the “link-name” to “ak4637-device”. This has no significance unless equivalent driver change is made. This is generally used if codec specific clock setup is needed at init time or at runtime. You can refer to section driver update for custom audio card to understand what this really means.

Thanks,
Sameer.

18

I got lucky and added log.txt the output of trace I think.

You asked for this.

mediainfo ./cheering.wav
General
Complete name : ./cheering.wav
Format : Wave
File size : 48.6 KiB
Duration : 4 s 514 ms
Overall bit rate mode : Constant
Overall bit rate : 88.3 kb/s

Audio
Format : PCM
Format settings : Unsigned
Codec ID : 1
Duration : 4 s 514 ms
Bit rate mode : Constant
Bit rate : 88.2 kb/s
Channel(s) : 1 channel
Sampling rate : 11.025 kHz
Bit depth : 8 bits
Stream size : 48.6 KiB (100%)

Please explain more about link-name and what it normally points to, I just made up the name, having no doc on what it points to.

Thanks,
Terry

19

results:
Playing WAVE ‘./cheering.wav’ : Unsigned 8 bit, Rate 11025 Hz, Mono
clock enable_cnt prepare_cnt rate req_rate accuracy phase

gpc2clk 1 1 0 0 0 0
*[ default_freq 0]
gpcclk 1 1 1300500000 1300500000 0 0
*[ default_freq 0]
vi 0 0 409600000 408000000 0 0
*[ default_freq 0]
isp 0 0 768000000 768000000 0 0
*[ default_freq 0]
sce_cpu_nic 1 1 115200000 115200000 0 0
*[ default_freq 0]
se 0 0 601600000 601600000 0 0
*[ default_freq 0]
sor1_pad_clkout 3 3 148500000 148500000 0 0
*[ default_freq 0]
sor1_out 2 2 148500000 24000000 0 0
*[ default_freq 0]
eqos_rx_input 1 1 0 0 0 0
*[ default_freq 0]
eqos_rx 1 1 0 0 0 0
*[ default_freq 0]
axi_cbb 1 1 115200000 115200000 0 0
*[ default_freq 0]
i2s6_sync_input 0 0 0 0 0 0
*[ default_freq 0]
i2s5_sync_input 0 0 0 0 0 0
*[ default_freq 0]
i2s4_sync_input 0 0 0 0 0 0
*[ default_freq 0]
i2s3_sync_input 0 0 0 0 0 0
*[ default_freq 0]
i2s2_sync_input 0 0 0 0 0 0
*[ default_freq 0]
i2s1_sync_input 0 0 176400 176400 0 0
*[ default_freq 0]
dspk2_sync_clk 0 0 176400 0 0 0
*[ default_freq 0]
dspk1_sync_clk 0 0 176400 0 0 0
*[ default_freq 0]
dmic4_sync_clk 0 0 176400 0 0 0
*[ default_freq 0]
dmic3_sync_clk 0 0 176400 0 0 0
*[ default_freq 0]
dmic2_sync_clk 0 0 176400 0 0 0
*[ default_freq 0]
dmic1_sync_clk 0 0 176400 0 0 0
*[ default_freq 0]
spdifin_sync_input 0 0 0 0 0 0
*[ default_freq 0]
i2s6_sync_clk 0 0 0 0 0 0
*[ default_freq 0]
i2s5_sync_clk 0 0 0 0 0 0
*[ default_freq 0]
i2s4_sync_clk 0 0 0 0 0 0
*[ default_freq 0]
i2s3_sync_clk 0 0 0 0 0 0
*[ default_freq 0]
i2s2_sync_clk 0 0 0 0 0 0
*[ default_freq 0]
i2s1_sync_clk 0 0 0 0 0 0
*[ default_freq 0]
32khz_out0 0 0 32768 32768 0 0
*[ default_freq 0]
nvjpg 0 0 857600000 857600000 0 0
*[ default_freq 0]
nvenc 0 0 1164800000 1164800000 0 0
*[ default_freq 0]
vic 0 0 1024000000 4294967295 0 0
*[ default_freq 0]
nvdec 0 0 1203200000 1203200000 0 0
*[ default_freq 0]
tsecb 0 0 716800000 716800000 0 0
*[ default_freq 0]
tsec 0 0 716800000 716800000 0 0
*[ default_freq 0]
emc 0 0 1600000000 1600000000 0 0
*[ default_freq 0]
osc 2 2 38400000 38400000 0 0
*[ default_freq 0]
spi2 0 0 38400000 38400000 0 0
*[ default_freq 0]
nafll_disp 0 0 0 0 0 0
*[ default_freq 0]
dflldisp_div 0 0 0 0 0 0
*[ default_freq 0]
pwm4 1 1 38400000 38400000 0 0
*[ default_freq 0]
usb2_hsic_trk 1 1 9600000 9600000 0 0
*[ default_freq 0]
usb2_trk 1 1 9600000 9600000 0 0
*[ default_freq 0]
clk_m 7 7 19200000 19200000 0 0
*[ default_freq 0]
spi1 0 0 200000 200000 0 0
*[ default_freq 0]
hda2hdmicodec 2 2 19200000 19200000 0 0
*[ default_freq 0]
spi3 0 0 19200000 19200000 0 0
*[ default_freq 0]
dsib_lp 0 0 19200000 19200000 0 0
*[ default_freq 0]
dsia_lp 0 0 19200000 19200000 0 0
*[ default_freq 0]
nvdisplay_p2 2 2 19200000 19200000 0 0
*[ default_freq 0]
cec 1 1 19200000 19200000 0 0
*[ default_freq 0]
actmon 2 2 19200000 19200000 0 0
*[ default_freq 0]
mipi_cal 1 1 19200000 19200000 0 0
*[ default_freq 0]
fuse 2 2 19200000 19200000 0 0
*[ default_freq 0]
kfuse 0 0 19200000 19200000 0 0
*[ default_freq 0]
dbgapb 0 0 19200000 19200000 0 0
*[ default_freq 0]
clk_32k 0 0 32768 32768 0 0
*[ default_freq 0]
pll_ref 8 8 38400000 38400000 0 0
*[ default_freq 0]
pll_nvcsi 0 0 450000000 450000000 0 0
*[ default_freq 0]
nvcsi 0 0 225000000 225000000 0 0
*[ default_freq 0]
pll_c4_vco 0 0 784999218 784999218 0 0
*[ default_freq 0]
pll_c4_out0 0 0 196249804 196249804 0 0
*[ default_freq 0]
sdmmc4 0 0 196249804 196249804 0 0
*[ default_freq 0]
pll_c4_vco_div2 0 0 392499609 392499609 0 0
*[ default_freq 0]
pll_c4_out2 0 0 156999843 156999843 0 0
*[ default_freq 0]
pll_c4_out1 0 0 261666406 261666406 0 0
*[ default_freq 0]
pll_c4_out_mux 0 0 261666406 261666406 0 0
*[ default_freq 0]
pllc4_out 0 0 261666406 261666406 0 0
*[ default_freq 0]
pll_disphub 1 1 508800000 508800000 0 0
*[ default_freq 0]
plldisphub_div 0 0 508800000 508800000 0 0
*[ default_freq 0]
nvdisplayhub 2 2 23127272 22931252 0 0
*[ default_freq 0]
pll_d3 0 0 25806426 25806426 0 0
*[ default_freq 0]
pll_d2 2 2 148500000 148500000 0 0
*[ default_freq 0]
sor1 1 1 148500000 148500000 0 0
*[ default_freq 0]
nvdisplay_p1 4 4 148500000 148500000 0 0
*[ default_freq 0]
nvdisplay_disp 2 2 148500000 194000000 0 0
*[ default_freq 0]
pll_d 2 2 387996093 387996000 0 0
*[ default_freq 0]
dsib 1 1 387996093 582000000 0 0
*[ default_freq 0]
pll_d_out1 2 2 387996093 582000000 0 0
*[ default_freq 0]
dsi 1 1 387996093 582000000 0 0
*[ default_freq 0]
nvdisplay_p0 3 3 32333007 32333000 0 0
*[ default_freq 0]
nvdisplay_dsc 1 1 32333007 194000000 0 0
*[ default_freq 0]
pll_e 1 1 38400000 38400000 0 0
*[ default_freq 0]
pcie 0 0 38400000 38400000 0 0
*[ default_freq 0]
pll_a1 1 1 600000000 600000000 0 0
*[ default_freq 0]
pll_a_out1 1 1 150000000 150000000 0 0
*[ default_freq 0]
ape 3 3 150000000 150000000 0 0
*[ default_freq 0]
apb2ape 1 1 150000000 150000000 0 0
*[ default_freq 0]
pll_a_vco 1 1 258000000 258000000 0 0
*[ default_freq 0]
pll_a 1 1 270950390 270950400 0 0
*[ default_freq 0]
pll_a_out0 2 2 22579199 22579200 0 0
*[ default_freq 0]
dspk2 0 0 11289599 12288000 0 0
*[ default_freq 0]
dspk1 0 0 11289599 12288000 0 0
*[ default_freq 0]
dmic4 0 0 2508799 3072000 0 0
*[ default_freq 0]
dmic3 0 0 2508799 3072000 0 0
*[ default_freq 0]
dmic2 0 0 2508799 3072000 0 0
*[ default_freq 0]
dmic1 0 0 2508799 3072000 0 0
*[ default_freq 0]
i2s6 0 0 2052654 1536000 0 0
*[ default_freq 0]
i2s5 0 0 2052654 1536000 0 0
*[ default_freq 0]
i2s4 0 0 2052654 1536000 0 0
*[ default_freq 0]
i2s3 0 0 2052654 1536000 0 0
*[ default_freq 0]
i2s2 0 0 2052654 1536000 0 0
*[ default_freq 0]
i2s1 1 1 176399 176400 0 0
*[ default_freq 0]
ahub 2 2 22579199 22579200 0 0
*[ default_freq 0]
pll_c2 0 0 307200000 307200000 0 0
*[ default_freq 0]
pll_u 3 3 38400000 38400000 0 0
*[ default_freq 0]
pll_u_48M 1 1 48000000 48000000 0 0
*[ default_freq 0]
xusb_fs 2 2 48000000 48000000 0 0
*[ default_freq 0]
pll_u_480M 1 1 480000000 480000000 0 0
*[ default_freq 0]
xusb_core_ss 1 1 120000000 120000000 0 0
*[ default_freq 0]
pll_refe_ref 1 1 60000000 60000000 0 0
*[ default_freq 0]
pllrefe_iddq 1 1 60000000 60000000 0 0
*[ default_freq 0]
pll_refe 1 1 625000000 625000000 0 0
*[ default_freq 0]
pll_refe_out1 3 3 625000000 625000000 0 0
*[ default_freq 0]
eqos_tx_clk 1 1 125000000 125000000 0 0
*[ default_freq 0]
eqos_ptp_ref_clk 1 1 125000000 125000000 0 0
*[ default_freq 0]
pllrefe_out1_div5 1 1 125000000 125000000 0 0
*[ default_freq 0]
eqos_axi_clk 1 1 125000000 125000000 0 0
*[ default_freq 0]
pll_refe_out 0 0 312500000 312500000 0 0
*[ default_freq 0]
pllrefe_out_gated 0 0 312500000 312500000 0 0
*[ default_freq 0]
pll_aon 0 0 480000000 480000000 0 0
*[ default_freq 0]
pll_c 0 0 307200000 307200000 0 0
*[ default_freq 0]
pll_p 4 4 408000000 408000000 0 0
*[ default_freq 0]
pll_p_out5 1 1 204000000 204000000 0 0
*[ default_freq 0]
gpu 1 1 204000000 204000000 0 0
*[ default_freq 0]
sata_oob 0 0 204000000 204000000 0 0
*[ default_freq 0]
pll_p_div17 1 1 24000000 24000000 0 0
*[ default_freq 0]
sor_safe 2 2 24000000 24000000 0 0
*[ default_freq 0]
dpaux1 0 0 24000000 24000000 0 0
*[ default_freq 0]
host1x 1 1 102000000 102000000 0 0
*[ default_freq 0]
pll_p_out0 21 21 408000000 408000000 0 0
*[ default_freq 0]
spi4 0 0 4975610 5000000 0 0
*[ default_freq 0]
extperiph1 0 0 24000000 24000000 0 0
*[ default_freq 0]
nvcsilp 0 0 204000000 204000000 0 0
*[ default_freq 0]
aud_mclk 1 1 3175097 2822400 0 0
*[ default_freq 0]
sce_apb 1 1 102000000 102000000 0 0
*[ default_freq 0]
hda2codec_2x 2 2 48000000 48000000 0 0
*[ default_freq 0]
hda 2 2 51000000 51000000 0 0
*[ default_freq 0]
sdmmc1 0 0 204000000 204000000 0 0
*[ default_freq 0]
sdmmc3 0 0 3175098 101661 0 0
*[ default_freq 0]
sdmmc_legacy_tm 0 0 12000000 12000000 0 0
*[ default_freq 0]
xusb_core_dev 1 1 102000000 102000000 0 0
*[ default_freq 0]
xusb_falcon 1 1 204000000 204000000 0 0
*[ default_freq 0]
xusb 2 2 102000000 102000000 0 0
*[ default_freq 0]
xusb_ss 2 2 102000000 102000000 0 0
*[ default_freq 0]
xusb_host 1 1 102000000 102000000 0 0
*[ default_freq 0]
sata 0 0 102000000 102000000 0 0
*[ default_freq 0]
uartg 1 1 153614 153600 0 0
*[ default_freq 0]
uartd 0 0 408000000 19200000 0 0
*[ default_freq 0]
uartc 1 1 920994 921600 0 0
*[ default_freq 0]
uartb 0 0 408000000 19200000 0 0
*[ default_freq 0]
uarta 1 1 408000000 408000000 0 0
*[ default_freq 0]
spdif_in 0 0 408000000 408000000 0 0
*[ default_freq 0]
afi 0 0 3187500 0 0 0
*[ default_freq 0]
pwm3 1 1 102000000 102000000 0 0
*[ default_freq 0]
pwm2 0 0 102000000 102000000 0 0
*[ default_freq 0]
pwm1 1 1 102000000 102000000 0 0
*[ default_freq 0]
uart_fst_mipi_cal 1 1 68000000 68000000 0 0
*[ default_freq 0]
i2c9 1 1 20400000 20700000 0 0
*[ default_freq 0]
i2c8 1 1 81600000 83200000 0 0
*[ default_freq 0]
i2c7 1 1 81600000 83200000 0 0
*[ default_freq 0]
i2c6 1 1 20400000 20700000 0 0
*[ default_freq 0]
i2c4 1 1 20400000 20700000 0 0
*[ default_freq 0]
i2c3 1 1 81600000 83200000 0 0
*[ default_freq 0]
i2c2 1 1 81600000 83200000 0 0
*[ default_freq 0]
i2c1 1 1 20400000 20700000 0 0
*[ default_freq 0]
pllp_grtcba 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_grtbb 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_xusb 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_uphy 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_audio 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_grtcab 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_boot 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_grtcaa 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_grtlb 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_grtla 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_grtba 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_grtcbb 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_display 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_grttb 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_grtta 0 0 408000000 408000000 0 0
*[ default_freq 0]
pllp_aon 0 0 408000000 408000000 0 0
*[ default_freq 0]

Terry

20

i2s1__reg_dump (585 Bytes)

21

It seems like “aud_mclk” clock gets enabled but the rate is not correct (expected rate = 256 * sample rate = 11025 * 256 = 2822400). It can be noted that the requested rate is 2822400, but the rate it is set to is 3175097. If you had attached the clk summary log file, the parent and child clock relationships can be easily understood.

For example, below is the snippet of clock summary.

pll_a_vco                                               0            0   258000000   258000000          0 0
    *[        default_freq                                       0]
       pll_a                                                0            0   270950390   270950400          0 0
       *[        default_freq                                       0]
          pll_a_out0                                        0            0    45158398    45158400          0 0
          *[        default_freq                                       0]
             aud_mclk                                       0            0    11289599    11289600          0 0
             *[        default_freq                                       0]
             dspk2                                          0            0    11289599    12288000          0 0
             *[        default_freq                                       0]
             dspk1                                          0            0    11289599    12288000          0 0
             *[        default_freq                                       0]
             dmic4                                          0            0     3010559     3072000          0 0
             *[        default_freq                                       0]
             dmic3                                          0            0     3010559     3072000          0 0
             *[        default_freq                                       0]
             dmic2                                          0            0     3010559     3072000          0 0
             *[        default_freq                                       0]
             dmic1                                          0            0     3010559     3072000          0 0
             *[        default_freq                                       0]
             i2s6                                           0            0     2150399     1536000          0 0
             *[        default_freq                                       0]
             i2s5                                           0            0     2150399     1536000          0 0
             *[        default_freq                                       0]
             i2s4                                           0            0     2150399     1536000          0 0
             *[        default_freq                                       0]
             i2s3                                           0            0     2150399     1536000          0 0
             *[        default_freq                                       0]
             i2s2                                           0            0     2150399     1536000          0 0
             *[        default_freq                                       0]
             i2s1                                           0            0     1411199     1411200          0 0
             *[        default_freq                                       0]

This is just for illustration purpose. Don’t worry about the rates or clock enable state. Check the clock relationships. Both ‘i2s1’ and ‘aud_mclk’ have ‘pll_a_out0’ as their parent.

Do you see below?

root@tegra-ubuntu:~# cat /sys/kernel/debug/bpmp/debug/clk/aud_mclk/parent
pll_a_out0

If not, the parent should be updated to pll_a_out0. Try if below helps.

# echo pll_a_out0 > /sys/kernel/debug/bpmp/debug/clk/aud_mclk/parent
# cat /sys/kernel/debug/bpmp/debug/clk/aud_mclk/parent

The Tegra BSP does not support unsigned format. But since you have used ‘plughw’ in aplay command, I believe this gets converted to a supported S8 format by ALSA plugin. But still the ‘i2s1’ clock does not appear fine.

Expected rate = channel * bits * sample rate = 1 * 8 * 11025 = 88200

But the rate you see is ~176400, which is wrong.

Is your use case strictly requires 1-channel, 8-bit and 11025 Hz?

If not, can you try once with 2-channel, 16-bit and 48000 Hz stream?
With this stream you can expect following rates:
aud_mclk = 12288000 Hz
i2s1 = 1536000 Hz

I am not sure if you checked the section I mentioned in my earlier replies ( driver update for custom audio card)
It has details about what needs to be done from driver side. But it depends on whether your codec requires some init time or run time support.

I am still looking for your codec driver and data sheet. Please attach it in your next reply.

22

The file plays just fine on hdmi,

This is what is on my system.
sudo cat /sys/kernel/debug/bpmp/debug/clk/aud_mclk/parent
pll_p_out0

ak4637_linux_driver_190527.ZIP (983.5 KB)
ak4637_ALSA LinuxDriver_f04e.pdf (888.1 KB)
AK4637EN.pdf (1.9 MB)

Think this is what you requested.

s your use case strictly requires 1-channel, 8-bit and 11025 Hz?

If not, can you try once with 2-channel, 16-bit and 48000 Hz stream?
With this stream you can expect following rates:
aud_mclk = 12288000 Hz
i2s1 = 1536000 Hz

How do I do this for you, I just picked 1,0 because of amixer -c tegrasndt186ref cset name=“I2S1 Mux” “ADMAIF1”

because I had a script that tried all aplay -l devices and 1,0 is the only one that caused anything to show up in syslog

aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: tegrahda [tegra-hda], device 3: HDMI 0 [HDMI 0]
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: tegrahda [tegra-hda], device 7: HDMI 0 [HDMI 0]
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 0: ADMAIF1 CIF ADMAIF1-0
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 1: ADMAIF2 CIF ADMAIF2-1
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 2: ADMAIF3 CIF ADMAIF3-2
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 3: ADMAIF4 CIF ADMAIF4-3
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 4: ADMAIF5 CIF ADMAIF5-4
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 5: ADMAIF6 CIF ADMAIF6-5
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 6: ADMAIF7 CIF ADMAIF7-6
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 7: ADMAIF8 CIF ADMAIF8-7
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 8: ADMAIF9 CIF ADMAIF9-8
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 9: ADMAIF10 CIF ADMAIF10-9
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 10: ADMAIF11 CIF ADMAIF11-10
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 11: ADMAIF12 CIF ADMAIF12-11
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 12: ADMAIF13 CIF ADMAIF13-12
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 13: ADMAIF14 CIF ADMAIF14-13
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 14: ADMAIF15 CIF ADMAIF15-14
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 15: ADMAIF16 CIF ADMAIF16-15
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 16: ADMAIF17 CIF ADMAIF17-16
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 17: ADMAIF18 CIF ADMAIF18-17
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 18: ADMAIF19 CIF ADMAIF19-18
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: tegrasndt186ref [tegra-snd-t186ref-mobile-rt565x], device 19: ADMAIF20 CIF ADMAIF20-19
Subdevices: 1/1
Subdevice #0: subdevice #0

I personally have zero experience with aplay and audio. I can build drivers and add them to the device tree, only if I can find something that makes sense to copy from another forum topic or device tree.

That is why I asked for a cookbook/faq that might give me all the info I need to know and understand to do this task.

Terry

23

So I figured since link-name was not needed to remove it from my device tree, bad move on my part, now the system kernel crashes and reboots continuously,

Please remember that link-name is needed for the system to boot.

Terry

24

was able to undo the link-name crash.

You need anything else from me? Any more feedback?

Thanks,
Terry