Hi,professor.
I’m using jetson tx2 i2s1 to output audio data.
I need four signals(MCLK,BCLK,LRCLK,DATA).
I check the schematic to make sure the following connections.
J21
Pin7: MCLK
Pin12: BCLK
Pin35: LRCLK
Pin40: DATA
when I issue following command in Shell, BCLK/LRCLK/DATA are okay, but MCLK no signal!
amixer -c tegrasndt186ref sset "ADMAIF1 Mux" "I2S1"
aplay -D hw:tegrasndt186ref,0 dream.wav
I need MCLK to drive other parts. Please help me.
Need I change the kernel code or the dts file ? how to change.
please help me. thanks very much.
attached information:
I used SDKManager JetPack4.2.2(REV.1) to flush jetson-tx2.
Jetson OS image file system and OS version is 32.2.
Drivers for jetson tx2 version is 32.2.
Nothing was changed!
please help me.
I check the pinctrl reg.
sudo grep mclk /sys/kernel/debug/tegra_pinctrl_reg
Bank:0 Reg:0x02431020 Val:0x00000059 -> aud_mclk_pj4
could someone guide me how to do?
The image version is
head -n 1 /etc/nv_tegra_release
#R32 (release) ,REVISION:2.1, GCID:16294929,BOARD:t186ref,EABI:aarch64,DATE: Tue Aug 13 04:45:36 UTC 2019
I checked the 《Parker_TRM_DP07821001p.pdf》 file
8.31.7.9 PADCTL_AUDIO_AUD_MCLK_0
Offset: 0x20 | Read/Write: R/W | SCR Protection: SCR_AUD_MCLK_0 | Reset: 0x00000454
Bit Reset Description
12 DISABLE E_SCHMT:
0 = DISABLE
1 = ENABLE
11 DISABLE E_OD:
0 = DISABLE
1 = ENABLE
10 HSIO GPIO_SF_SEL:
0 = GPIO
1 = HSIO
8 DISABLE E_LPDR:
0 = DISABLE
1 = ENABLE
6 ENABLE E_INPUT:
0 = DISABLE
1 = ENABLE
4 TRISTATE TRISTATE:
0 = PASSTHROUGH
1 = TRISTATE
3:2 PULL_DOWN PUPD:
0 = NONE
1 = PULL_DOWN
2 = PULL_UP
3 = RSVD
[b]1:0 AUD PM:
0 = AUD[/b]
1 = RSVD1
2 = RSVD2
3 = RSVD3
So I use the following command to change it dynamically.
sudo busybox devmem 0x02431020 32 0x00000058
Then I issue
aplay -D hw:tegrasndt186ref,0 dream.wav
MCLK can’t probe any signal yet!
so i check again
sudo grep mclk /sys/kernel/debug/tegra_pinctrl_reg
Bank:0 Reg:0x02431020 Val:0x00000058 -> aud_mclk_pj4
The last 2 bits was changed. This means PADCTL_AUDIO_AUD_MCLK_0[1:0]=00
Why I can’t probe signal on MCLK physical pin ?
sudo grep dap1 /sys/kernel/debug/tegra_pinctrl_reg
Bank: 0 Reg: 0x02431028 Val:0x00000400 -> dap1_fs_pj3
Bank: 0 Reg: 0x02431030 Val:0x00000458 -> dap1_din_pj2
Bank: 0 Reg: 0x02431038 Val:0x00000400 -> dap1_dout_pj1
Bank: 0 Reg: 0x02431040 Val:0x00000400 -> dap1_sclk_pj0
could someone meet this situation?
Hello!
The value 0x58 enable the tristate bit which disables the output driver on the pin and enables the input. You want to disable the tristate and you do not need to enable the input and so you should try setting to 0x08 instead and see if this works.
Regards,
Jon
Dear jonathanh，I followed your advise. But no signal output on MCLK(J21 Pin7) yet.
I executed commands:
sudo busybox devmem 0x02431020 32 0x00000008
amixer -c tegrasndt186ref sset "ADMAIF1 Mux" "I2S1"
aplay -D hw:tegrasndt186ref,0 dream.wav
But I can probe BCLK/LRCLK/DATA.
could you guide me more detail? thanks.
Hello!
After running the aplay command do you see that the aud_mclk is active …
$ sudo cat /sys/kernel/debug/clk/clk_summary
...
pll_a_vco 1 1 258000000 258000000 0 0
*[ default_freq 0]
pll_a 1 1 245759960 245760000 0 0
*[ default_freq 0]
pll_a_out0 3 3 49151992 49152000 0 0
*[ default_freq 0]
aud_mclk 1 1 12287998 12288000
By default it’s parent clock should be the pll_a_out0 as shown above.
Regards,
Jon
Dear jonathanh,
I execute aplay command and then checked clk_summary file at once, it seems aud_mclk is enabled.
but could you tell me what I am missing ?
I am not familar with jetson tx2.
thank you very much.
yntp16@yntp16:~$ sudo cat /sys/kernel/debug/clk/clk_summary
[sudo] password for yntp16:
clock enable_cnt prepare_cnt rate req_rate accuracy phase
----------------------------------------------------------------------------------------------------------------------
pll_a_vco 1 1 258000000 258000000 0 0
*[ default_freq 0]
pll_a 1 1 270950390 270950400 0 0
*[ default_freq 0]
pll_a_out0 3 3 45158398 45158400 0 0
*[ default_freq 0]
i2s1 1 1 1411199 1411200 0 0
*[ default_freq 0]
aud_mclk 1 1 11289599 11289600 0 0
Hello!
Did you check this while aplay is running? Sorry before I said ‘after’ but I meant after you starting aplay then dump the clocks. By default while aplay is running, it should be enabled. If it is not then have you modified the audio machine driver in anyway?
Regards,
Jon
Dear jonathanh，
Yes. The wav file is big enough. it can play long time. so I have enough time to check clk_summary file while aplay is running.
I found aud_mclk is enabled while aplay running, disabled while aplay stop.
And I am not edit any driver codes in kernel source.
I don’t know how to do next. MCLK pin no signal.But the pinmux setting is okay.
hope god bless me.
thanks for your patient.
Am I missing something ?
hi jonathanh!
From the TRM datasheet, It seems AUD_MCLK is not belongs to I2S part. AUD_MCLK can be drived alonely.
And now i2s part works well, only missing AUD_MCLK.
Could you guide me how to drive AUD_MCLK ? which register should be configured?
Hello!
Yes that is right the AUD_MCLK is separate from the I2S interface. The Tegra audio driver enables it when audio is active by default.
I checked your register configuration again for the AUD_MCLK and we need to set bit 10 in the register (so it is not a GPIO) so please try …
sudo busybox devmem 0x02431020 32 0x00000408
Regards,
Jon
It works!
thank you very much, jonathanh!
You are my god!